Datasheet MCP6071, MCP6072, MCP6074 (Microchip) - 7
| 制造商 | Microchip |
| 描述 | The MCP6071 operational amplifier (op amps) has a low input offset voltage (±150 µV, maximum) and rail-to-rail input and output operation |
| 页数 / 页 | 40 / 7 — MCP6071/2/4. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 14%. 1000. 1244 … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
MCP6071/2/4. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 14%. 1000. 1244 Samples. 12%. 800. VDD = 6.0V. Representative Part. VDD = 3.0V
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MCP6071/2/4 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
14% s 1000 e 1244 Samples ) 12% V 800 VDD = 6.0V Representative Part nc VDD = 3.0V re VCM = VDD/3 (µ 600 u 10% e c g 400 c a 8% lt O 200 o of V 0 6% et ge -200 ta ffs 4% T n -400 A = -40°C e t O TA = +25°C rc u -600 2% T e p A = +85°C P In -800 TA = +125°C 0% -1000 0 0 0 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 -9 -6 -3 30 60 90 -1 -120 120 150 -0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. Input Offset Voltage (µV) Common Mode Input Voltage (V) FIGURE 2-1:
Input Offset Voltage with
FIGURE 2-4:
Input Offset Voltage vs. VDD = 3.0V. Common Mode Input Voltage with VDD = 6.0V.
27% 1000 ) 24% 1244 Samples V ces V 800 V DD = 3.0V Representative Part DD = 3.0V µ 21% ( 600 ren VCM = VDD/3 e 400 cu 18% TA = -40°C to +85°C ag lt 200 15% o f Oc 0 t V 12% e o e -200 g a 9% ffs T -400 A = -40°C t O TA = +25°C 6% -600 T rcent pu A = +85°C e 3% -800 In TA = +125°C P 0% -1000 1 4 7 0 3 6 9 2 5 8 1 4 -8 -4 0 4 8 .5 .2 -20 -16 -12 12 16 20 -0 -0 0. 0. 0. 1. 1. 1. 1. 2. 2. 2. 3. 3. Input Offset Drift with Temperature (µV/°C) Common Mode Input Voltage (V) FIGURE 2-2:
Input Offset Voltage Drift
FIGURE 2-5:
Input Offset Voltage vs. with VDD = 3.0V and TA ≤ +85°C. Common Mode Input Voltage with VDD = 3.0V.
27% 1000 ) ces 1244 Samples 24% 800 VDD = 1.8V Representative Part n VDD = 3.0V 21% re V (µV 600 CM = VDD/3 e cu 18% TA = +85°C to +125°C 400 c ltag 15% 200 o f O o 0 12% t V e e g -200 9% T ta ffs A = -40°C -400 T 6% O A = +25°C -600 T rcen A = +85°C 3% e Input -800 T P A = +125°C 0% -1000 2 1 7 9 -20 -16 -1 -8 -4 0 4 8 12 16 20 .5 .3 .1 -0 -0 -0 0. 0.3 0.5 0. 0.9 1.1 1.3 1.5 1.7 1. 2.1 2.3 Input Offset Drift with Temperature (µV/°C) Common Mode Input Voltage (V) FIGURE 2-3:
Input Offset Voltage Drift
FIGURE 2-6:
Input Offset Voltage vs. with VDD = 3.0V and TA ≥ +85°C. Common Mode Input Voltage with VDD = 1.8V. © 2010 Microchip Technology Inc. DS22142B-page 7 Document Outline MCP6071/2/4 Features Applications Design Aids Typical Application Description Package Types Notes: 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC electrical specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: temperature specifications Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C. 1.3 Test Circuits EQUATION 1-1: FIGURE 1-1: AC and DC Test Circuit for Most Specifications. Notes: 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage with VDD = 3.0V. FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA £ +85°C. FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA ³ +85°C. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 3.0V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-9: Input Noise Voltage Density vs. Frequency. FIGURE 2-10: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-11: CMRR, PSRR vs. Frequency. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Common Mode Input Voltage Range Limit vs. Ambient Temperature. FIGURE 2-14: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-15: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs Ambient Temperature with VCM = 0.9VDD. FIGURE 2-17: Quiescent Current vs. Power Supply Voltage with VCM = 0.9VDD. FIGURE 2-18: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-19: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-20: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-21: Channel-to-Channel Separation vs. Frequency ( MCP6072/4 only). FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-25: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-26: Output Voltage Swing vs. Frequency. FIGURE 2-27: Ratio of Output Voltage Headroom to Output Current vs. Output Current. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Slew Rate vs. Ambient Temperature. FIGURE 2-30: Small Signal Non-Inverting Pulse Response. FIGURE 2-31: Small Signal Inverting Pulse Response. FIGURE 2-32: Large Signal Non-Inverting Pulse Response. FIGURE 2-33: Large Signal Inverting Pulse Response. FIGURE 2-34: The MCP6071/2/4 Shows No Phase Reversal. FIGURE 2-35: Closed Loop Output Impedance vs. Frequency. FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) Notes: 4.0 Application Information 4.1 Rail-to-Rail Input 4.1.1 Phase ReversaL 4.1.2 Input Voltage Limits FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.1.3 Input Current Limits FIGURE 4-3: Protecting the Analog Inputs. 4.1.4 Normal Operation 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 1. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. 2. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. 4.7 Application Circuits 4.7.1 Gyrator FIGURE 4-8: Gyrator. 4.7.2 Instrumentation Amplifier FIGURE 4-9: Two Op Amp Instrumentation Amplifier. 4.7.3 Precision Comparator FIGURE 4-10: Precision, Non-inverting Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes Notes: 6.0 Packaging Information 6.1 Package Marking Information 110 µA, High Precision Op Amps Appendix A: REVISION HISTORY Revision B (December 2010) 1. Added new SOT-23-5 package type for MCP6071 device. 2. Corrected Figures 2-13, 2-22, 2-23, 2-24, 2-28, 2-29 and 2-34 in Section 2.0 “Typical Performance Curves”. 3. Modified Table 3-1 to show the pin column for MCP6071, SOT-23-5 package. 4. Updated Section 4.1.2 “Input Voltage Limits”. 5. Added Section 4.1.3 “Input Current Limits”. 6. Added new document item in Section 5.5 “Application Notes”. 7. Updated the Product Identification System page. Revision A (March 2009) Notes: a) MCP6071T-E/OT: Tape and Reel, 5LD SOT-23 pkg b) MCP6071-E/SN: 8LD SOIC pkg c) MCP6071T-E/SN: Tape and Reel, 8LD SOIC pkg d) MCP6071T-E/MNY: Tape and Reel, 8LD 2x3 TDFN pkg a) MCP6072-E/SN: 8LD SOIC pkg b) MCP6072T-E/SN: Tape and Reel, 8LD SOIC pkg c) MCP6072T-E/MNY: Tape and Reel 8LD 2x3 TDFN pkg a) MCP6074-E/SL: 14LD SOIC pkg b) MCP6074T-E/SL: Tape and Reel, 14LD SOIC pkg c) MCP6074-E/ST: 14LD TSSOP pkg d) MCP6074T-E/ST: Tape and Reel, 14LD TSSOP pkg Notes: Worldwide Sales and Service Trademarks Worldwide Sales
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
14% s 1000 e 1244 Samples ) 12% V 800 VDD = 6.0V Representative Part nc VDD = 3.0V re VCM = VDD/3 (µ 600 u 10% e c g 400 c a 8% lt O 200 o of V 0 6% et ge -200 ta ffs 4% T n -400 A = -40°C e t O TA = +25°C rc u -600 2% T e p A = +85°C P In -800 TA = +125°C 0% -1000 0 0 0 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 -9 -6 -3 30 60 90 -1 -120 120 150 -0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. Input Offset Voltage (µV) Common Mode Input Voltage (V) FIGURE 2-1:
Input Offset Voltage with
FIGURE 2-4:
Input Offset Voltage vs. VDD = 3.0V. Common Mode Input Voltage with VDD = 6.0V.
27% 1000 ) 24% 1244 Samples V ces V 800 V DD = 3.0V Representative Part DD = 3.0V µ 21% ( 600 ren VCM = VDD/3 e 400 cu 18% TA = -40°C to +85°C ag lt 200 15% o f Oc 0 t V 12% e o e -200 g a 9% ffs T -400 A = -40°C t O TA = +25°C 6% -600 T rcent pu A = +85°C e 3% -800 In TA = +125°C P 0% -1000 1 4 7 0 3 6 9 2 5 8 1 4 -8 -4 0 4 8 .5 .2 -20 -16 -12 12 16 20 -0 -0 0. 0. 0. 1. 1. 1. 1. 2. 2. 2. 3. 3. Input Offset Drift with Temperature (µV/°C) Common Mode Input Voltage (V) FIGURE 2-2:
Input Offset Voltage Drift
FIGURE 2-5:
Input Offset Voltage vs. with VDD = 3.0V and TA ≤ +85°C. Common Mode Input Voltage with VDD = 3.0V.
27% 1000 ) ces 1244 Samples 24% 800 VDD = 1.8V Representative Part n VDD = 3.0V 21% re V (µV 600 CM = VDD/3 e cu 18% TA = +85°C to +125°C 400 c ltag 15% 200 o f O o 0 12% t V e e g -200 9% T ta ffs A = -40°C -400 T 6% O A = +25°C -600 T rcen A = +85°C 3% e Input -800 T P A = +125°C 0% -1000 2 1 7 9 -20 -16 -1 -8 -4 0 4 8 12 16 20 .5 .3 .1 -0 -0 -0 0. 0.3 0.5 0. 0.9 1.1 1.3 1.5 1.7 1. 2.1 2.3 Input Offset Drift with Temperature (µV/°C) Common Mode Input Voltage (V) FIGURE 2-3:
Input Offset Voltage Drift
FIGURE 2-6:
Input Offset Voltage vs. with VDD = 3.0V and TA ≥ +85°C. Common Mode Input Voltage with VDD = 1.8V. © 2010 Microchip Technology Inc. DS22142B-page 7 Document Outline MCP6071/2/4 Features Applications Design Aids Typical Application Description Package Types Notes: 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC electrical specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: temperature specifications Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C. 1.3 Test Circuits EQUATION 1-1: FIGURE 1-1: AC and DC Test Circuit for Most Specifications. Notes: 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage with VDD = 3.0V. FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA £ +85°C. FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA ³ +85°C. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 3.0V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-9: Input Noise Voltage Density vs. Frequency. FIGURE 2-10: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-11: CMRR, PSRR vs. Frequency. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Common Mode Input Voltage Range Limit vs. Ambient Temperature. FIGURE 2-14: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-15: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs Ambient Temperature with VCM = 0.9VDD. FIGURE 2-17: Quiescent Current vs. Power Supply Voltage with VCM = 0.9VDD. FIGURE 2-18: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-19: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-20: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-21: Channel-to-Channel Separation vs. Frequency ( MCP6072/4 only). FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-25: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-26: Output Voltage Swing vs. Frequency. FIGURE 2-27: Ratio of Output Voltage Headroom to Output Current vs. Output Current. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Slew Rate vs. Ambient Temperature. FIGURE 2-30: Small Signal Non-Inverting Pulse Response. FIGURE 2-31: Small Signal Inverting Pulse Response. FIGURE 2-32: Large Signal Non-Inverting Pulse Response. FIGURE 2-33: Large Signal Inverting Pulse Response. FIGURE 2-34: The MCP6071/2/4 Shows No Phase Reversal. FIGURE 2-35: Closed Loop Output Impedance vs. Frequency. FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) Notes: 4.0 Application Information 4.1 Rail-to-Rail Input 4.1.1 Phase ReversaL 4.1.2 Input Voltage Limits FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.1.3 Input Current Limits FIGURE 4-3: Protecting the Analog Inputs. 4.1.4 Normal Operation 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 1. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. 2. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. 4.7 Application Circuits 4.7.1 Gyrator FIGURE 4-8: Gyrator. 4.7.2 Instrumentation Amplifier FIGURE 4-9: Two Op Amp Instrumentation Amplifier. 4.7.3 Precision Comparator FIGURE 4-10: Precision, Non-inverting Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes Notes: 6.0 Packaging Information 6.1 Package Marking Information 110 µA, High Precision Op Amps Appendix A: REVISION HISTORY Revision B (December 2010) 1. Added new SOT-23-5 package type for MCP6071 device. 2. Corrected Figures 2-13, 2-22, 2-23, 2-24, 2-28, 2-29 and 2-34 in Section 2.0 “Typical Performance Curves”. 3. Modified Table 3-1 to show the pin column for MCP6071, SOT-23-5 package. 4. Updated Section 4.1.2 “Input Voltage Limits”. 5. Added Section 4.1.3 “Input Current Limits”. 6. Added new document item in Section 5.5 “Application Notes”. 7. Updated the Product Identification System page. Revision A (March 2009) Notes: a) MCP6071T-E/OT: Tape and Reel, 5LD SOT-23 pkg b) MCP6071-E/SN: 8LD SOIC pkg c) MCP6071T-E/SN: Tape and Reel, 8LD SOIC pkg d) MCP6071T-E/MNY: Tape and Reel, 8LD 2x3 TDFN pkg a) MCP6072-E/SN: 8LD SOIC pkg b) MCP6072T-E/SN: Tape and Reel, 8LD SOIC pkg c) MCP6072T-E/MNY: Tape and Reel 8LD 2x3 TDFN pkg a) MCP6074-E/SL: 14LD SOIC pkg b) MCP6074T-E/SL: Tape and Reel, 14LD SOIC pkg c) MCP6074-E/ST: 14LD TSSOP pkg d) MCP6074T-E/ST: Tape and Reel, 14LD TSSOP pkg Notes: Worldwide Sales and Service Trademarks Worldwide Sales