Datasheet MCP6V06, MCP6V07, MCP6V08 (Microchip) - 3

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MCP6V06/7/8 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings †
VDD – VSS ...6.5V
† Notice:
Stresses above those listed under “Absolute Current at Input Pins ..±2 mA Maximum Ratings” may cause permanent damage to the Analog Inputs (V device. This is a stress rating only and functional operation of IN+ and VIN–) †† ... VSS – 1.0V to VDD+1.0V the device at those or any other conditions above those All other Inputs and Outputs .. VSS – 0.3V to VDD+0.3V indicated in the operational listings of this specification is not Difference Input voltage .. |VDD – VSS| implied. Exposure to maximum rating conditions for extended Output Short Circuit Current .. Continuous periods may affect device reliability. Current at Output and Supply Pins ..±30 mA
††
See
Section 4.2.1 “Rail-to-Rail Inputs”
. Storage Temperature ...-65°C to +150°C Max. Junction Temperature .. +150°C ESD protection on all pins (HBM, MM) ..≥ 4 kV, 300V
1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL, and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage VOS -3 — +3 µV TA = +25°C
(Note 1)
Input Offset Voltage Drift with Temperature TC1 -50 — +50 nV/°C TA = -40 to +125°C (linear Temp. Co.)
(Note 1 )
Input Offset Voltage Quadratic Temp. Co. TC2 — ±0.15 — nV/°C2 TA = -40 to +125°C Power Supply Rejection PSRR 125 142 — dB
(Note 1 ) Input Bias Current and Impedance
Input Bias Current IB — +6 — pA Input Bias Current across Temperature IB — +140 — pA TA = +85°C IB — +1500 +5000 pA TA = +125°C Input Offset Current IOS — -85 — pA Input Offset Current across Temperature IOS — -85 — pA TA = +85°C IOS -1000 -190 1000 pA TA = +125°C Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||6 — Ω
||
pF
Common Mode
Common-Mode Input Voltage Range VCMR VSS − 0.20 — VDD + 0.20 V
(Note 2 )
Common-Mode Rejection CMRR 120 136 — dB VDD = 1.8V, VCM = -0.2V to 2.0V (
Note 1, Note 2)
CMRR 130 147 — dB VDD = 5.5V, VCM = -0.2V to 5.7V (
Note 1, Note 2) Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 125 147 — dB VDD = 1.8V, VOUT = 0.2V to 1.6V
(Note 1 )
AOL 135 158 — dB VDD = 5.5V, VOUT = 0.2V to 5.3V
(Note 1 ) Note 1:
Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts can only be screened in production (except TC1; see
Appendix B: “Offset Related Test Screens”
).
2:
Figure 2-18 shows how VCMR changed across temperature for the first three production lots. © 2008 Microchip Technology Inc. DS22093B-page 3 Document Outline 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications (Continued) TABLE 1-2: AC Electrical Specifications TABLE 1-3: Digital Electrical Specifications TABLE 1-4: Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. FIGURE 1-4: Chip Select (MCP6V08). 1.4 Test Circuits FIGURE 1-5: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-6: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-7: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Quadratic Temp Co. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_L. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_H. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 1.8V. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-9: CMRR. FIGURE 2-10: PSRR. FIGURE 2-11: DC Open-Loop Gain. FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85˚C. FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125˚C. FIGURE 2-16: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-17: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-19: Output Voltage Headroom vs. Output Current. FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-22: Supply Current vs. Power Supply Voltage. FIGURE 2-23: Power On Reset Trip Voltage. FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-25: CMRR and PSRR vs. Frequency. FIGURE 2-26: Open-Loop Gain vs. Frequency with VDD = 1.8V. FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 5.5V. FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-31: Closed-Loop Output Impedance vs. Frequency with VDD = 1.8V. FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. FIGURE 2-33: Channel-to-Channel Separation vs. Frequency. FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-35: Input Noise Voltage Density vs. Frequency. FIGURE 2-36: Input Noise Voltage Density vs. Input Common Mode Voltage. FIGURE 2-37: Inter-Modulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-7). FIGURE 2-38: Inter-Modulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-7). FIGURE 2-39: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =1.8V. FIGURE 2-40: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =5.5V. 2.5 Time Response FIGURE 2-41: Input Offset Voltage vs. Time with Temperature Change. FIGURE 2-42: Input Offset Voltage vs. Time at Power Up. FIGURE 2-43: The MCP6V06/7/8 family shows no input phase reversal with overdrive. FIGURE 2-44: Non-inverting Small Signal Step Response. FIGURE 2-45: Non-inverting Large Signal Step Response. FIGURE 2-46: Inverting Small Signal Step Response. FIGURE 2-47: Inverting Large Signal Step Response. FIGURE 2-48: Slew Rate vs. Ambient Temperature. FIGURE 2-49: Output Overdrive Recovery vs. Time with G = -100 V/V. FIGURE 2-50: Output Overdrive Recovery Time vs. Inverting Gain. 2.6 Chip Select Response (MCP6V08 only) FIGURE 2-51: Chip Select Current vs. Power Supply Voltage. FIGURE 2-52: Power Supply Current vs. Chip Select Voltage with VDD = 1.8V. FIGURE 2-53: Power Supply Current vs. Chip Select Voltage with VDD = 5.5V. FIGURE 2-54: Chip Select Current vs. Chip Select Voltage. FIGURE 2-55: Chip Select Voltage, Output Voltage vs. Time with VDD = 1.8V. FIGURE 2-56: Chip Select Voltage, Output Voltage vs. Time with VDD = 5.5V. FIGURE 2-57: Chip Select Relative Logic Thresholds vs. Ambient Temperature. FIGURE 2-58: Chip Select Hysteresis. FIGURE 2-59: Chip Select Turn On Time vs. Ambient Temperature. FIGURE 2-60: Chip Select’s Pull-down Resistor (RPD) vs. Ambient Temperature. FIGURE 2-61: Quiescent Current in Shutdown vs. Power Supply Voltage. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Chip Select (CS) Digital Input 3.5 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Overview of Auto-zeroing Operation FIGURE 4-1: Simplified Auto-zeroed Op Amp Functional Diagram. FIGURE 4-2: Normal Mode of Operation (f1); Equivalent Amplifier Diagram. FIGURE 4-3: Auto-zeroing Mode of Operation (f2); Equivalent Diagram. 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs. 4.3 Application Tips FIGURE 4-6: Output Resistor, RISO, Stabilizes Capacitive Loads. FIGURE 4-7: Recommended RISO values for Capacitive Loads. FIGURE 4-8: Output Load Issue. FIGURE 4-9: One Solution To Output Load Issue. FIGURE 4-10: Additional Supply Filtering. FIGURE 4-11: PCB Layout and Schematic for Single Non-inverting and Inverting Amplifiers. FIGURE 4-12: PCB Layout and Schematic for Single Difference Amplifier. FIGURE 4-13: PCB Layout and Schematic for Dual Non-inverting Amplifier. FIGURE 4-14: PCB Layout for Individual Resistors. 4.4 Typical Applications FIGURE 4-15: Simple Design. FIGURE 4-16: High Performance Design. FIGURE 4-17: RTD Sensor. FIGURE 4-18: Thermocouple Sensor; Simplified Circuit. FIGURE 4-19: Thermocouple Sensor. FIGURE 4-20: Offset Correction. FIGURE 4-21: Precision Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information