Datasheet MCP6V71, MCP6V71U, MCP6V72, MCP6V74 (Microchip)

link to page 17
MCP6V71/1U/2/4 170 µA, 2 MHz Zero-Drift Op Amps Features Description
• High DC Precision: The Microchip Technology Inc. MCP6V71/1U/2/4 - VOS Drift: ±15 nV/°C (maximum, VDD = 5.5V) family of operational amplifiers provides input offset - V voltage correction for very low offset and offset drift. OS: ±8 µV (maximum) - A These are low-power devices with a gain bandwidth OL: 126 dB (minimum, VDD = 5.5V) product of 2 MHz (typical). They are unity-gain stable, - PSRR: 115 dB (minimum, VDD = 5.5V) have virtually no 1/f noise and have good Power Supply - CMRR: 117 dB (minimum, VDD = 5.5V) Rejection Ratio (PSRR) and Common Mode Rejection - Eni: 0.45 µVP-P (typical), f = 0.1 Hz to 10 Hz Ratio (CMRR). These products operate with a single - E supply voltage as low as 2V, while drawing ni: 0.15 µVP-P (typical), f = 0.01 Hz to 1 Hz • Enhanced EMI Protection: 170 µA/amplifier (typical) of quiescent current. - Electromagnetic Interference Rejection Ratio The MCP6V71/1U/2/4 family has enhanced EMI pro- (EMIRR) at 1.8 GHz: 96 dB tection to minimize any electromagnetic interference • Low Power and Supply Voltages: from external sources. This feature makes it well suited for EMI sensitive applications such as power lines, - IQ: 170 µA/amplifier (typical) radio stations and mobile communications, etc. - Wide Supply Voltage Range: 2V to 5.5V The Microchip Technology Inc. MCP6V71/1U/2/4 op • Smal Packages: amps are offered in single (MCP6V71 and - Singles in SC70, SOT-23 MCP6V71U), dual (MCP6V72) and quad (MCP6V74) - Duals in MSOP-8, 2x3 TDFN packages. They were designed using an advanced - Quads in TSSOP-14 CMOS process. • Easy to Use: - Rail-to-Rail Input/Output
Package Types
- Gain Bandwidth Product: 2 MHz (typical)
MCP6V71 MCP6V72
- Unity Gain Stable SOT-23 MSOP • Extended Temperature Range: -40°C to +125°C VOUT 1 5 VDD V 1 8 V OUTA DD
Typical Applications
V V SS 2 VINA– 2 7 OUTB • Portable Instrumentation VIN+ 3 4 VIN– VINA+ 3 6 VINB– • Sensor Conditioning VSS 4 5 VINB+ • Temperature Measurement
MCP6V71U MCP6V72
• DC Offset Correction SC70, SOT-23 2×3 TDFN * • Medical Instrumentation V V V IN+ 1 5 VDD OUTA 1 8 DD
Design Aids
V V 2 EP 7 V SS 2 INA– OUTB • FilterLab® Software V V 3 9 6 V IN– 3 4 VOUT INA+ INB– • Microchip Advanced Part Selector (MAPS) VSS 4 5 VINB+ • Analog Demonstration and Evaluation Boards • Application Notes
MCP6V74
TSSOP
Related Parts
V 1 14 V OUTA OUTD • MCP6V11/1U/2/4: Zero-Drift, Low Power V V INA– 2 13 IND– • MCP6V31/1U/2/4 VINA+ 3 12 VIND+ • MCP6V61/1U: Zero-Drift 1 MHz VDD 4 11 VSS • MCP6V81/1U: Zero-Drift, 5 MHz V V INB+ 5 10 INC+ • MCP6V91/1U: Zero-Drift, 10 MHz VINB– 6 9 VINC– VOUTB 7 8 VOUTC * Includes Exposed Thermal Pad (EP); see Table 3-1.  2015 Microchip Technology Inc. DS20005385B-page 1 Document Outline Features Typical Applications Design Aids Related Parts Description Package Types Typical Application Circuit 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications (Continued) TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. 1.4 Test Circuits FIGURE 1-4: AC and DC Test Circuit for Most Noninverting Gain Conditions. FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-6: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCML. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMH. FIGURE 2-6: Input Offset Voltage vs. Output Voltage with VDD = 2.0V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage with VDD = 5.5V. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-10: Common Mode Rejection Ratio. FIGURE 2-11: Power Supply Rejection Ratio. FIGURE 2-12: DC Open-Loop Gain. FIGURE 2-13: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-16: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-17: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-18: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-19: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Supply Current vs. Power Supply Voltage. FIGURE 2-24: Power-On Reset Trip Voltage. FIGURE 2-25: Power-On Reset Voltage vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-26: CMRR and PSRR vs. Frequency. FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 2V. FIGURE 2-28: Open-Loop Gain vs. Frequency with VDD = 5.5V. FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-31: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 2V. FIGURE 2-33: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-35: EMIRR vs Frequency. FIGURE 2-36: EMIRR vs RF Input Peak Voltage. FIGURE 2-37: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-38: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. FIGURE 2-39: Input Noise Voltage Density vs. Input Common Mode Voltage. FIGURE 2-40: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-6). FIGURE 2-41: Intermodulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-6). FIGURE 2-42: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 2V. FIGURE 2-43: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 5.5V. 2.5 Time Response FIGURE 2-44: Input Offset Voltage vs. Time with Temperature Change. FIGURE 2-45: Input Offset Voltage vs. Time at Power-Up. FIGURE 2-46: The MCP6V71/1U/2/4 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-47: Non-inverting Small Signal Step Response. FIGURE 2-48: Non-inverting Large Signal Step Response. FIGURE 2-49: Inverting Small Signal Step Response. FIGURE 2-50: Inverting Large Signal Step Response. FIGURE 2-51: Slew Rate vs. Ambient Temperature. FIGURE 2-52: Output Overdrive Recovery vs. Time with G = -10 V/V. FIGURE 2-53: Output Overdrive Recovery Time vs. Inverting Gain. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Overview of Zero-Drift Operation FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram. FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram. 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. FIGURE 4-6: Protecting the Analog Inputs Against High Currents. 4.3 Application Tips FIGURE 4-7: Output Resistor, RISO, Stabilizes Capacitive Loads. FIGURE 4-8: Recommended RISO values for Capacitive Loads. FIGURE 4-9: Output Load. FIGURE 4-10: Amplifier with Parasitic Capacitance. 4.4 Typical Applications FIGURE 4-11: Simple Design. FIGURE 4-12: RTD Sensor. FIGURE 4-13: Offset Correction. FIGURE 4-14: Precision Comparator. 5.0 Design Aids 5.1 FilterLab® Software 5.2 Microchip Advanced Part Selector (MAPS) 5.3 Analog Demonstration and Evaluation Boards 5.4 Application Notes 6.0 Packaging Information 6.1 Package Marking Information 170 µA, 2 MHz Zero-Drift Op Amps Appendix A: Revision History Revision B (September 2015) Revision A (March 2015) Product Identification System AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Worldwide Sales and Service