Datasheet MCP621S, MCP621S, MCP622, MCP623, MCP624, MCP625, MCP629 (Microchip) - 5

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MCP621/1S/2/3/4/5/9 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters Sym. Min. Typ. Max. Units Conditions CAL/CS Low Specifications
CAL/CS Logic Threshold, Low VIL VSS — 0.2VDD V CAL/CS Input Current, Low ICSL — 0 — nA CAL/CS = 0V
CAL/CS High Specifications
CAL/CS Logic Threshold, High VIH 0.8VDD VDD V CAL/CS Input Current, High ICSH — 0.7 — µA CAL/CS = VDD GND Current ISS -3.5 -1.8 — µA Single, CAL/CS = VDD = 2.5V ISS -8 -4 — µA Single, CAL/CS = VDD = 5.5V ISS -5 -2.5 — µA Dual, CAL/CS = VDD = 2.5V ISS -10 -5 — µA Dual, CAL/CS = VDD = 5.5V CAL/CS Internal Pull-Down RPD — 5 — M Resistor Amplifier Output Leakage IO(LEAK) — 50 — nA CAL/CS = VDD, TA = 125°C
POR Dynamic Specifications
VDD Low to Amplifier Off Time tPOFF — 200 — ns G = +1 V/V, VL = VSS, (output goes High Z) VDD = 2.5V to 0V step to VOUT = 0.1 (2.5V) VDD High to Amplifier On Time tPON 100 200 300 ms G = +1 V/V, VL = VSS, (including calibration) VDD = 0V to 2.5V step to VOUT = 0.9 (2.5V)
CAL/CS Dynamic Specifications
CAL/CS Input Hysteresis V — HYST 0.25 — V CAL/CS Setup Time tCSU 1 — — µs G = +1 V/V, VL = VSS
(Notes 2, 3, 4 )
(between CAL/CS edges) CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2) CAL/CS High to Amplifier Off Time tCOFF — 200 — ns G = +1 V/V, VL = VSS, (output goes High Z) CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2) CAL/CS Low to Amplifier On Time tCON — 3 4 ms G = +1 V/V, VL = VSS, MCP621 and (including calibration) MCP625, CAL/CS = 0.2VDD to VOUT = 0.9 (VDD/2) tCON — 6 8 ms G = +1 V/V, VL = VSS, MCP629, CAL/CS = 0.2VDD to VOUT = 0.9 (VDD/2)
Note 1:
The MCP622 single, MCP625 dual and MCP629 quad have their CAL/CS inputs internally pulled down to VSS (0V).
2:
This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised before the calibration is complete, the calibration will be aborted and the part will return to Low-Power mode.
3:
For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously (within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in Calibration mode; allow more than the maximum tCON time (4 ms) before the other side is toggled.
4:
For the MCP629 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultaneously (within a time much smaller than tCSU) to make all four op amps perform the same function simultaneously, and the maximum tCON time is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD (CALBC/CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in Calibration mode; allow more than the maximum tCON time (8 ms) before the other side is toggled.  2009-2014 Microchip Technology Inc. DS20002188D-page 5 Document Outline 20 MHz, 200 µV Op Amps with mCal Features Typical Applications Design Aids Description Typical Application Circuit High Gain-Bandwidth Op Amp Portfolio Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Digital Electrical Specifications TABLE 1-4: Temperature Specifications 1.3 Timing Diagram FIGURE 1-1: Timing Diagram. 1.4 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves 2.1 DC Signal Inputs FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Repeatability (repeated calibration). FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Low Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-7: High Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-10: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-11: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-15: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-16: Ratio of Output Voltage Headroom to Output Current. FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-18: Output Short-Circuit Current vs. Power Supply Voltage. FIGURE 2-19: Supply Current vs. Power Supply Voltage. FIGURE 2-20: Supply Current vs. Common Mode Input Voltage. FIGURE 2-21: Power-On Reset Voltages vs. Ambient Temperature. FIGURE 2-22: Normalized Internal Calibration Voltage. FIGURE 2-23: VCAL Input Resistance vs. Temperature. 2.3 Frequency Response FIGURE 2-24: CMRR and PSRR vs. Frequency. FIGURE 2-25: Open-Loop Gain vs. Frequency. FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-27: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-29: Closed-Loop Output Impedance vs. Frequency. FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load. FIGURE 2-31: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-32: Input Noise Voltage Density vs. Frequency. FIGURE 2-33: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz. FIGURE 2-34: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz. FIGURE 2-35: Input Noise plus Offset vs. Time with 0.1 Hz Filter. FIGURE 2-36: THD+N vs. Frequency. 2.5 Time Response FIGURE 2-37: Non-Inverting Small Signal Step Response. FIGURE 2-38: Non-Inverting Large Signal Step Response. FIGURE 2-39: Inverting Small Signal Step Response. FIGURE 2-40: Inverting Large Signal Step Response. FIGURE 2-41: The MCP621/1S/2/3/4/5/9 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-42: Slew Rate vs. Ambient Temperature. FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency. 2.6 Calibration and Chip Select Response FIGURE 2-44: CAL/CS Current vs. Power Supply Voltage. FIGURE 2-45: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 2.5V. FIGURE 2-46: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 5.5V. FIGURE 2-47: CAL/CS Hysteresis vs. Ambient Temperature. FIGURE 2-48: CAL/CS Turn-On Time vs. Ambient Temperature. FIGURE 2-49: CAL/CS’s Pull-Down Resistor (RPD) vs. Ambient Temperature. FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage. FIGURE 2-51: Output Leakage Current vs. Output Voltage. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Calibration Common Mode Voltage Input 3.5 Calibrate/Chip Select Digital Input 3.6 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Calibration and Chip Select FIGURE 4-1: Common-Mode Reference’s Input Circuitry. FIGURE 4-2: Setting VCM with External Resistors. 4.2 Input FIGURE 4-3: Simplified Analog Input ESD Structures. FIGURE 4-4: Protecting the Analog Inputs. FIGURE 4-5: Unity Gain Voltage Limitations for Linear Operation. 4.3 Rail-to-Rail Output FIGURE 4-6: Output Current. FIGURE 4-7: Diagram for Resistive Load Power Calculations. FIGURE 4-8: Diagram for Capacitive Load Power Calculations. 4.4 Improving Stability FIGURE 4-9: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-10: Recommended RISO Values for Capacitive Loads. FIGURE 4-11: Amplifier with Parasitic Capacitance. FIGURE 4-12: Maximum Recommended RF vs. Gain. 4.5 Power Supply 4.6 High Speed PCB Layout 4.7 Typical Applications FIGURE 4-13: Power Driver. FIGURE 4-14: Transimpedance Amplifier for an Optical Detector. FIGURE 4-15: H-Bridge Driver. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service