1. Features
Core ̶ ARM Cortex-M3 revision 2.0 running at up to 84 MHz ̶ Memory Protection Unit (MPU) ̶ Thumb-2 instruction set ̶ 24-bit SysTick Counter ̶ Nested Vector Interrupt Controller Memories ̶ 256 to 512 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank ̶ 32 to 100 Kbytes embedded SRAM with dual banks ̶ 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines ̶ Static Memory Controller (SMC): SRAM, NOR, NAND support. NFC with 4 Kbyte RAM buffer and ECC System ̶ Embedded voltage regulator for single supply operation ̶ Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe reset ̶ Quartz or ceramic resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock ̶ High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for fast device startup ̶ Slow Clock Internal RC oscillator as permanent clock for device clock in low-power mode ̶ One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Mini Host/Device ̶ Temperature Sensor ̶ Up to 17 peripheral DMA (PDC) channels and 6-channel central DMA plus dedicated DMA for High-Speed USB Mini Host/Device and Ethernet MAC Low-power Modes ̶ Sleep, Wait and Backup modes, down to 2.5 µA in Backup mode with RTC, RTT, and GPBR Peripherals ̶ USB 2.0 Device/Mini Host: 480 Mbps, 4 Kbyte FIFO, up to 10 bidirectional Endpoints, dedicated DMA ̶ Up to 4 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester and LIN support) and one UART ̶ 2 TWI (I2C compatible), up to 6 SPIs, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) with up to 2 slots ̶ 9-channel 32-bit Timer Counter (TC) for capture, compare and PWM mode, Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor ̶ Up to 8-channel 16-bit PWM (PWMC) with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control ̶ 32-bit low-power Real-time Timer (RTT) and low-power Real-time Clock (RTC) with calendar and alarm features ̶ 256-bit General Purpose Backup Registers (GPBR) ̶ 16-channel 12-bit 1 msps ADC with differential input mode and programmable gain stage ̶ 2-channel 12-bit 1 msps DAC ̶ Ethernet MAC 10/100 (EMAC) with dedicated DMA ̶ 2 CAN Controllers with 8 Mailboxes ̶ True Random Number Generator (TRNG) ̶ Register Write Protection I/O ̶ Up to 103 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on- die Series Resistor Termination ̶ Up to six 32-bit Parallel Input/Outputs (PIO) 2 SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15 Document Outline Description 1. Features 1.1 Configuration Summary 2. SAM3X/A Block Diagram 3. Signal Description 3.1 Design Considerations 4. Package and Pinout 4.1 SAM3A4/8C and SAM3X4/8C Package and Pinout 4.1.3 100-lead LQFP Pinout 4.1.4 100-ball TFBGA Pinout 4.2 SAM3X4/8E Package and Pinout 4.2.3 144-lead LQFP Pinout 4.2.4 144-ball LFBGA Pinout 5. Power Considerations 5.1 Power Supplies 5.2 Power-up Considerations 5.2.1 VDDIO Versus VDDCORE 5.2.2 VDDIO Versus VDDIN 5.3 Voltage Regulator 5.4 Typical Powering Schematics 5.5 Active Mode 5.6 Low Power Modes 5.6.1 Backup Mode 5.6.2 Wait Mode 5.6.3 Sleep Mode 5.6.4 Low Power Mode Summary Table 5.7 Wake-up Sources 5.8 Fast Startup 6. Input/Output Lines 6.1 General Purpose I/O Lines (GPIO) 6.2 System I/O Lines 6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins 6.3 Test Pin 6.4 NRST Pin 6.5 NRSTB Pin 6.6 ERASE Pin 7. Memories 7.1 Product Mapping 7.2 Embedded Memories 7.2.1 Internal SRAM 7.2.2 Internal ROM 7.2.3 Embedded Flash 7.2.3.1 Flash Overview 7.2.3.2 Flash Power Supply 7.2.3.3 Enhanced Embedded Flash Controller 7.2.3.4 Lock Regions 7.2.3.5 Security Bit Feature 7.2.3.6 Calibration Bits 7.2.3.7 Unique Identifier 7.2.3.8 Fast Flash Programming Interface (FFPI) 7.2.3.9 SAM-BA Boot 7.2.3.10 GPNVM Bits 7.2.4 Boot Strategies 7.3 External Memories 7.3.1 External Memory Bus 7.3.2 Static Memory Controller 7.3.3 NAND Flash Controller 7.3.4 NAND Flash Error Corrected Code Controller 7.3.5 SDR-SDRAM Controller (217-pin SAM3X8H(l) only) 8. System Controller 8.1 System Controller and Peripherals Mapping 8.2 Power-on-Reset, Brownout and Supply Monitor 8.2.1 Power-on-Reset on VDDBU 8.2.2 Brownout Detector on VDDCORE 8.2.3 Supply Monitor on VDDUTMI 9. Peripherals 9.1 Peripheral Identifiers 9.2 APB/AHB Bridge 9.3 Peripheral Signal Multiplexing on I/O Lines 9.3.1 PIO Controller A Multiplexing 9.3.2 PIO Controller B Multiplexing 9.3.3 PIO Controller C Multiplexing 9.3.4 PIO Controller D Multiplexing 9.3.5 PIO Controller E Multiplexing 9.3.6 PIO Controller F Multiplexing 10. ARM Cortex® M3 Processor 10.1 About this section 10.2 Embedded Characteristics 10.3 About the Cortex-M3 processor and core peripherals 10.3.1 System level interface 10.3.2 Integrated configurable debug 10.3.3 Cortex-M3 processor features and benefits summary 10.3.4 Cortex-M3 core peripherals 10.3.4.1 Nested Vectored Interrupt Controller 10.3.4.2 System control block 10.3.4.3 System timer 10.3.4.4 Memory protection unit 10.4 Programmers model 10.4.1 Processor mode and privilege levels for software execution 10.4.1.1 Thread mode 10.4.1.2 Handler mode 10.4.1.3 Unprivileged 10.4.1.4 Privileged 10.4.2 Stacks 10.4.3 Core registers 10.4.3.1 General-purpose registers 10.4.3.2 Stack Pointer 10.4.3.3 Link Register 10.4.3.4 Program Counter 10.4.3.5 Program Status Register 10.4.3.6 Application Program Status Register 10.4.3.7 Interrupt Program Status Register 10.4.3.8 Execution Program Status Register 10.4.3.9 Interruptible-continuable instructions 10.4.3.10 If-Then block 10.4.3.11 Exception mask registers 10.4.3.12 Priority Mask Register 10.4.3.13 Fault Mask Register 10.4.3.14 Base Priority Mask Register 10.4.3.15 CONTROL register 10.4.4 Exceptions and interrupts 10.4.5 Data types 10.4.6 The Cortex Microcontroller Software Interface Standard 10.5 Memory model 10.5.1 Memory regions, types and attributes 10.5.1.1 Normal 10.5.1.2 Device 10.5.1.3 Strongly-ordered 10.5.1.4 Shareable 10.5.1.5 Execute Never (XN) 10.5.2 Memory system ordering of memory accesses 10.5.3 Behavior of memory accesses 10.5.3.1 Additional memory access constraints for shared memory 10.5.4 Software ordering of memory accesses 10.5.4.1 DMB 10.5.4.2 DSB 10.5.4.3 ISB 10.5.5 Bit-banding 10.5.5.1 Directly accessing an alias region 10.5.5.2 Directly accessing a bit-band region 10.5.6 Memory endianness 10.5.6.1 Little-endian format 10.5.7 Synchronization primitives 10.5.7.1 A Load-Exclusive instruction 10.5.7.2 A Store-Exclusive instruction 10.5.8 Programming hints for the synchronization primitives 10.6 Exception model 10.6.1 Exception states 10.6.1.1 Inactive 10.6.1.2 Pending 10.6.1.3 Active 10.6.1.4 Active and pending 10.6.2 Exception types 10.6.2.1 Reset 10.6.2.2 Non Maskable Interrupt (NMI) 10.6.2.3 Hard fault 10.6.2.4 Memory management fault 10.6.2.5 Bus fault 10.6.2.6 Usage fault 10.6.2.7 SVCall 10.6.2.8 PendSV 10.6.2.9 SysTick 10.6.2.10 Interrupt (IRQ) 10.6.3 Exception handlers 10.6.3.1 Interrupt Service Routines (ISRs) 10.6.3.2 Fault handlers 10.6.3.3 System handlers 10.6.4 Vector table 10.6.5 Exception priorities 10.6.6 Interrupt priority grouping 10.6.7 Exception entry and return 10.6.7.1 Preemption 10.6.7.2 Return 10.6.7.3 Tail-chaining 10.6.7.4 Late-arriving 10.6.7.5 Exception entry 10.6.7.6 Exception return 10.7 Fault handling 10.7.1 Fault types 10.7.2 Fault escalation and hard faults 10.7.3 Fault status registers and fault address registers 10.7.4 Lockup 10.8 Power management 10.8.1 Entering sleep mode 10.8.1.1 Wait for interrupt 10.8.1.2 Wait for event 10.8.1.3 Sleep-on-exit 10.8.2 Wakeup from sleep mode 10.8.2.1 Wakeup from WFI or sleep-on-exit 10.8.2.2 Wakeup from WFE 10.8.3 Power management programming hints 10.9 Instruction set summary 10.10 Intrinsic functions 10.11 About the instruction descriptions 10.11.1 Operands 10.11.2 Restrictions when using PC or SP 10.11.3 Flexible second operand 10.11.3.1 Constant 10.11.3.2 Instruction substitution 10.11.3.3 Register with optional shift 10.11.4 Shift Operations 10.11.4.1 ASR 10.11.4.2 LSR 10.11.4.3 LSL 10.11.4.4 ROR 10.11.4.5 RRX 10.11.5 Address alignment 10.11.6 PC-relative expressions 10.11.7 Conditional execution 10.11.7.1 The condition flags 10.11.7.2 Condition code suffixes 10.11.7.3 Absolute value 10.11.7.4 Compare and update value 10.11.8 Instruction width selection 10.11.8.1 Instruction width selection 10.12 Memory access instructions 10.12.1 ADR 10.12.1.1 Syntax 10.12.1.2 Operation 10.12.1.3 Restrictions 10.12.1.4 Condition flags 10.12.1.5 Examples 10.12.2 LDR and STR, immediate offset 10.12.2.1 Syntax 10.12.2.2 Operation 10.12.2.3 Offset addressing 10.12.2.4 Pre-indexed addressing 10.12.2.5 Post-indexed addressing 10.12.2.6 Restrictions 10.12.2.7 Condition flags 10.12.2.8 Examples 10.12.3 LDR and STR, register offset 10.12.3.1 Syntax 10.12.3.2 Operation 10.12.3.3 Restrictions 10.12.3.4 Condition flags 10.12.3.5 Examples 10.12.4 LDR and STR, unprivileged 10.12.4.1 Syntax 10.12.4.2 Operation 10.12.4.3 Restrictions 10.12.4.4 Condition flags 10.12.4.5 Examples 10.12.5 LDR, PC-relative 10.12.5.1 Syntax 10.12.5.2 Operation 10.12.5.3 Restrictions 10.12.5.4 Condition flags 10.12.5.5 Examples 10.12.6 LDM and STM 10.12.6.1 Syntax 10.12.6.2 Operation 10.12.6.3 Restrictions 10.12.6.4 Condition flags 10.12.6.5 Examples 10.12.6.6 Incorrect examples 10.12.7 PUSH and POP 10.12.7.1 Syntax 10.12.7.2 Operation 10.12.7.3 Restrictions 10.12.7.4 Condition flags 10.12.7.5 Examples 10.12.8 LDREX and STREX 10.12.8.1 Syntax 10.12.8.2 Operation 10.12.8.3 Restrictions 10.12.8.4 Condition flags 10.12.8.5 Examples 10.12.9 CLREX 10.12.9.1 Syntax 10.12.9.2 Operation 10.12.9.3 Condition flags 10.12.9.4 Examples 10.13 General data processing instructions 10.13.1 ADD, ADC, SUB, SBC, and RSB 10.13.1.1 Syntax 10.13.1.2 Operation 10.13.1.3 Restrictions 10.13.1.4 Condition flags 10.13.1.5 Examples 10.13.1.6 Multiword arithmetic examples 10.13.1.7 64-bit addition 10.13.1.8 96-bit subtraction 10.13.2 AND, ORR, EOR, BIC, and ORN 10.13.2.1 Syntax 10.13.2.2 Operation 10.13.2.3 Restrictions 10.13.2.4 Condition flags 10.13.2.5 Examples 10.13.3 ASR, LSL, LSR, ROR, and RRX 10.13.3.1 Syntax 10.13.3.2 Operation 10.13.3.3 Restrictions 10.13.3.4 Condition flags 10.13.3.5 Examples 10.13.4 CLZ 10.13.4.1 Syntax 10.13.4.2 Operation 10.13.4.3 Restrictions 10.13.4.4 Condition flags 10.13.4.5 Examples 10.13.5 CMP and CMN 10.13.5.1 Syntax 10.13.5.2 Operation 10.13.5.3 Restrictions 10.13.5.4 Condition flags 10.13.5.5 Examples 10.13.6 MOV and MVN 10.13.6.1 Syntax 10.13.6.2 Operation 10.13.6.3 Restrictions 10.13.6.4 Condition flags 10.13.6.5 Example 10.13.7 MOVT 10.13.7.1 Syntax 10.13.7.2 Operation 10.13.7.3 Restrictions 10.13.7.4 Condition flags 10.13.7.5 Examples 10.13.8 REV, REV16, REVSH, and RBIT 10.13.8.1 Syntax 10.13.8.2 Operation 10.13.8.3 Restrictions 10.13.8.4 Condition flags 10.13.8.5 Examples 10.13.9 TST and TEQ 10.13.9.1 Syntax 10.13.9.2 Operation 10.13.9.3 Restrictions 10.13.9.4 Condition flags 10.13.9.5 Examples 10.14 Multiply and divide instructions 10.14.1 MUL, MLA, and MLS 10.14.1.1 Syntax 10.14.1.2 Operation 10.14.1.3 Restrictions 10.14.1.4 Condition flags 10.14.1.5 Examples 10.14.2 UMULL, UMLAL, SMULL, and SMLAL 10.14.2.1 Syntax 10.14.2.2 Operation 10.14.2.3 Restrictions 10.14.2.4 Condition flags 10.14.2.5 Examples 10.14.3 SDIV and UDIV 10.14.3.1 Syntax 10.14.3.2 Operation 10.14.3.3 Restrictions 10.14.3.4 Condition flags 10.14.3.5 Examples 10.15 Saturating instructions 10.15.1 SSAT and USAT 10.15.1.1 Syntax 10.15.1.2 Operation 10.15.1.3 Restrictions 10.15.1.4 Condition flags 10.15.1.5 Examples 10.16 Bitfield instructions 10.16.1 BFC and BFI 10.16.1.1 Syntax 10.16.1.2 Operation 10.16.1.3 Restrictions 10.16.1.4 Condition flags 10.16.1.5 Examples 10.16.2 SBFX and UBFX 10.16.2.1 Syntax 10.16.2.2 Operation 10.16.2.3 Restrictions 10.16.2.4 Condition flags 10.16.2.5 Examples 10.16.3 SXT and UXT 10.16.3.1 Syntax 10.16.3.2 Operation 10.16.3.3 Restrictions 10.16.3.4 Condition flags 10.16.3.5 Examples 10.17 Branch and control instructions 10.17.1 B, BL, BX, and BLX 10.17.1.1 Syntax 10.17.1.2 Operation 10.17.1.3 Restrictions 10.17.1.4 Condition flags 10.17.1.5 Examples 10.17.2 CBZ and CBNZ 10.17.2.1 Syntax 10.17.2.2 Operation 10.17.2.3 Restrictions 10.17.2.4 Condition flags 10.17.2.5 Examples 10.17.3 IT 10.17.3.1 Syntax 10.17.3.2 Operation 10.17.3.3 Restrictions 10.17.3.4 Condition flags 10.17.3.5 Example 10.17.4 TBB and TBH 10.17.4.1 Syntax 10.17.4.2 Operation 10.17.4.3 Restrictions 10.17.4.4 Condition flags 10.17.4.5 Examples 10.18 Miscellaneous instructions 10.18.1 BKPT 10.18.1.1 Syntax 10.18.1.2 Operation 10.18.1.3 Condition flags 10.18.1.4 Examples 10.18.2 CPS 10.18.2.1 Syntax 10.18.2.2 Operation 10.18.2.3 Restrictions 10.18.2.4 Condition flags 10.18.2.5 Examples 10.18.3 DMB 10.18.3.1 Syntax 10.18.3.2 Operation 10.18.3.3 Condition flags 10.18.3.4 Examples 10.18.4 DSB 10.18.4.1 Syntax 10.18.4.2 Operation 10.18.4.3 Condition flags 10.18.4.4 Examples 10.18.5 ISB 10.18.5.1 Syntax 10.18.5.2 Operation 10.18.5.3 Condition flags 10.18.5.4 Examples 10.18.6 MRS 10.18.6.1 Syntax 10.18.6.2 Operation 10.18.6.3 Restrictions 10.18.6.4 Condition flags 10.18.6.5 Examples 10.18.7 MSR 10.18.7.1 Syntax 10.18.7.2 Operation 10.18.7.3 Restrictions 10.18.7.4 Condition flags 10.18.7.5 Examples 10.18.8 NOP 10.18.8.1 Syntax 10.18.8.2 Operation 10.18.8.3 Condition flags 10.18.8.4 Examples 10.18.9 SEV 10.18.9.1 Syntax 10.18.9.2 Operation 10.18.9.3 Condition flags 10.18.9.4 Examples 10.18.10 SVC 10.18.10.1 Syntax 10.18.10.2 Operation 10.18.10.3 Condition flags 10.18.10.4 Examples 10.18.11 WFE 10.18.11.1 Syntax 10.18.11.2 Operation 10.18.11.3 Condition flags 10.18.11.4 Examples 10.18.12 WFI 10.18.12.1 Syntax 10.18.12.2 Operation 10.18.12.3 Condition flags 10.18.12.4 Examples 10.19 About the Cortex-M3 peripherals 10.20 Nested Vectored Interrupt Controller 10.20.1 The CMSIS mapping of the Cortex-M3 NVIC registers 10.20.2 Interrupt Set-enable Registers 10.20.3 Interrupt Clear-enable Registers 10.20.4 Interrupt Set-pending Registers 10.20.5 Interrupt Clear-pending Registers 10.20.6 Interrupt Active Bit Registers 10.20.7 Interrupt Priority Registers 10.20.7.1 IPRm 10.20.7.2 IPR4 10.20.7.3 IPR3 10.20.7.4 IPR2 10.20.7.5 IPR1 10.20.7.6 IPR0 10.20.8 Software Trigger Interrupt Register 10.20.9 Level-sensitive interrupts 10.20.9.1 Hardware and software control of interrupts 10.20.10 NVIC design hints and tips 10.20.10.1 NVIC programming hints 10.21 System control block 10.21.1 The CMSIS mapping of the Cortex-M3 SCB registers 10.21.2 Auxiliary Control Register 10.21.2.1 About IT folding 10.21.3 CPUID Base Register 10.21.4 Interrupt Control and State Register 10.21.5 Vector Table Offset Register 10.21.6 Application Interrupt and Reset Control Register 10.21.6.1 Binary point 10.21.7 System Control Register 10.21.8 Configuration and Control Register 10.21.9 System Handler Priority Registers 10.21.9.1 System Handler Priority Register 1 10.21.9.2 System Handler Priority Register 2 10.21.9.3 System Handler Priority Register 3 10.21.10 System Handler Control and State Register 10.21.11 Configurable Fault Status Register 10.21.11.1 Memory Management Fault Status Register 10.21.11.2 Bus Fault Status Register 10.21.11.3 Usage Fault Status Register 10.21.12 Hard Fault Status Register 10.21.13 Memory Management Fault Address Register 10.21.14 Bus Fault Address Register 10.21.15 System control block design hints and tips 10.22 System timer, SysTick 10.22.1 SysTick Control and Status Register 10.22.2 SysTick Reload Value Register 10.22.2.1 Calculating the RELOAD value 10.22.3 SysTick Current Value Register 10.22.4 SysTick Calibration Value Register 10.22.5 SysTick design hints and tips 10.23 Memory protection unit 10.23.1 MPU Type Register 10.23.2 MPU Control Register 10.23.3 MPU Region Number Register 10.23.4 MPU Region Base Address Register 10.23.4.1 The ADDR field 10.23.5 MPU Region Attribute and Size Register 10.23.5.1 SIZE field values 10.23.6 MPU access permission attributes 10.23.7 MPU mismatch 10.23.8 Updating an MPU region 10.23.8.1 Updating an MPU region using separate words 10.23.8.2 Updating an MPU region using multi-word writes 10.23.8.3 Subregions 10.23.8.4 Example of SRD use 10.23.9 MPU design hints and tips 10.23.9.1 MPU configuration for a microcontroller 10.24 Glossary 11. Debug and Test Features 11.1 Description 11.2 Embedded Characteristics 11.3 Application Examples 11.3.1 Debug Environment 11.3.2 Test Environment 11.4 Debug and Test Pin Description 11.5 Functional Description 11.5.1 Test Pin 11.5.2 Debug Architecture 11.5.3 Serial Wire/JTAG Debug Port (SWJ-DP) 11.5.3.1 SW-DP and JTAG-DP Selection Mechanism 11.5.4 FPB (Flash Patch Breakpoint) 11.5.5 DWT (Data Watchpoint and Trace) 11.5.6 ITM (Instrumentation Trace Macrocell) 11.5.6.1 How to Configure the ITM 11.5.6.2 Asynchronous Mode 11.5.6.3 5.4.3. How to Configure the TPIU 11.5.7 IEEE® 1149.1 JTAG Boundary Scan 11.5.7.1 JTAG Boundary-scan Register 11.5.8 ID Code Register 12. Reset Controller (RSTC) 12.1 Description 12.2 Embedded Characteristics 12.3 Block Diagram 12.4 Functional Description 12.4.1 Reset Controller Overview 12.4.2 NRST Manager 12.4.2.1 NRST Signal or Interrupt 12.4.2.2 NRST External Reset Control 12.4.3 Brownout Manager 12.4.4 Reset States 12.4.4.1 General Reset 12.4.4.2 Backup Reset 12.4.4.3 User Reset 12.4.4.4 Software Reset 12.4.4.5 Watchdog Reset 12.4.5 Reset State Priorities 12.4.6 Reset Controller Status Register 12.5 Reset Controller (RSTC) User Interface 12.5.1 Reset Controller Control Register 12.5.2 Reset Controller Status Register 12.5.3 Reset Controller Mode Register 13. Real-time Timer (RTT) 13.1 Description 13.2 Embedded Characteristics 13.3 Block Diagram 13.4 Functional Description 13.5 Real-time Timer (RTT) User Interface 13.5.1 Real-time Timer Mode Register 13.5.2 Real-time Timer Alarm Register 13.5.3 Real-time Timer Value Register 13.5.4 Real-time Timer Status Register 14. Real-time Clock (RTC) 14.1 Description 14.2 Embedded Characteristics 14.3 Block Diagram 14.4 Product Dependencies 14.4.1 Power Management 14.4.2 Interrupt 14.5 Functional Description 14.5.1 Reference Clock 14.5.2 Timing 14.5.3 Alarm 14.5.4 Error Checking 14.5.5 Updating Time/Calendar 14.6 Real-time Clock (RTC) User Interface 14.6.1 RTC Control Register 14.6.2 RTC Mode Register 14.6.3 RTC Time Register 14.6.4 RTC Calendar Register 14.6.5 RTC Time Alarm Register 14.6.6 RTC Calendar Alarm Register 14.6.7 RTC Status Register 14.6.8 RTC Status Clear Command Register 14.6.9 RTC Interrupt Enable Register 14.6.10 RTC Interrupt Disable Register 14.6.11 RTC Interrupt Mask Register 14.6.12 RTC Valid Entry Register 14.6.13 RTC Write Protect Mode Register 15. Watchdog Timer (WDT) 15.1 Description 15.2 Embedded Characteristics 15.3 Block Diagram 15.4 Functional Description 15.5 Watchdog Timer (WDT) User Interface 15.5.1 Watchdog Timer Control Register 15.5.2 Watchdog Timer Mode Register 15.5.3 Watchdog Timer Status Register 16. Supply Controller (SUPC) 16.1 Description 16.2 Embedded Characteristics 16.3 Block Diagram 16.4 Supply Controller Functional Description 16.4.1 Supply Controller Overview 16.4.2 Slow Clock Generator 16.4.3 Voltage Regulator Control/Backup Low Power Mode 16.4.4 Using Backup Batteries/Backup Supply 16.4.5 Supply Monitor 16.4.6 Backup Power Supply Reset 16.4.6.1 Raising the Backup Power Supply 16.4.6.2 NRSTB Asynchronous Reset Pin 16.4.6.3 SHDN output pin 16.4.7 Core Reset 16.4.7.1 Supply Monitor Reset 16.4.7.2 Brownout Detector Reset 16.4.8 Wake Up Sources 16.4.8.1 Force Wake Up 16.4.8.2 Wake Up Inputs 16.4.8.3 Clock Alarms 16.4.8.4 Supply Monitor Detection 16.5 Supply Controller (SUPC) User Interface 16.5.1 System Controller (SYSC) User Interface 16.5.2 System Controller (SYSC) User Interface 16.5.3 Supply Controller Control Register 16.5.4 Supply Controller Supply Monitor Mode Register 16.5.5 Supply Controller Mode Register 16.5.6 Supply Controller Wake Up Mode Register 16.5.7 System Controller Wake Up Inputs Register 16.5.8 Supply Controller Status Register 17. General Purpose Backup Registers (GPBR) 17.1 Description 17.2 Embedded Characteristics 17.3 General Purpose Backup Registers (GPBR) User Interface 17.3.1 General Purpose Backup Register x 18. Enhanced Embedded Flash Controller (EEFC) 18.1 Description 18.2 Embedded Characteristics 18.3 Product Dependencies 18.3.1 Power Management 18.3.2 Interrupt Sources 18.4 Functional Description 18.4.1 Embedded Flash Organization 18.4.3 Flash Commands 18.4.3.1 Getting Embedded Flash Descriptor 18.4.3.2 Write Commands 18.4.3.3 Erase Commands 18.4.3.4 Lock Bit Protection 18.4.3.5 GPNVM Bit 18.4.3.6 Calibration Bit 18.4.3.7 Security Bit Protection 18.4.3.8 Unique Identifier 18.5 Enhanced Embedded Flash Controller (EEFC) User Interface 18.5.1 EEFC Flash Mode Register 18.5.2 EEFC Flash Command Register 18.5.3 EEFC Flash Status Register 18.5.4 EEFC Flash Result Register 19. Fast Flash Programming Interface (FFPI) 19.1 Description 19.2 Parallel Fast Flash Programming 19.2.1 Device Configuration 19.2.2 Signal Names 19.2.3 Entering Programming Mode 19.2.4 Programmer Handshaking 19.2.4.1 Write Handshaking 19.2.4.2 Read Handshaking 19.2.5 Device Operations 19.2.5.1 Flash Read Command 19.2.5.2 Flash Write Command 19.2.5.3 Flash Full Erase Command 19.2.5.4 Flash Lock Commands 19.2.5.5 Flash General-purpose NVM Commands 19.2.5.6 Flash Security Bit Command 19.2.5.7 SAM3X/A Flash Select EEFC Command 19.2.5.8 Memory Write Command 19.2.5.9 Get Version Command 20. SAM3X/A Boot Program 20.1 Description 20.2 Flow Diagram 20.3 Device Initialization 20.4 SAM-BA Monitor 20.4.1 UART Serial Port 20.4.2 Xmodem Protocol 20.4.3 USB Device Port 20.4.3.1 Enumeration Process 20.4.3.2 Communication Endpoints 20.4.4 In Application Programming (IAP) Feature 20.5 Hardware and Software Constraints 21. Bus Matrix (MATRIX) 21.1 Description 21.2 Embedded Characteristics 21.2.1 Matrix Masters 21.2.2 Matrix Slaves 21.2.3 Master to Slave Access 21.3 Memory Mapping 21.4 Special Bus Granting Techniques 21.4.1 No Default Master 21.4.2 Last Access Master 21.4.3 Fixed Default Master 21.5 Arbitration 21.5.1 Arbitration Rules 21.5.1.1 Undefined Length Burst Arbitration 21.5.1.2 Slot Cycle Limit Arbitration 21.5.2 Round-Robin Arbitration 21.5.2.1 Round-Robin arbitration without default master 21.5.2.2 Round-Robin arbitration with last access master 21.5.2.3 Round-Robin arbitration with fixed default master 21.5.3 Fixed Priority Arbitration 21.6 System I/O Configuration 21.7 Write Protect Registers 21.8 Bus Matrix (MATRIX) User Interface 21.8.1 Bus Matrix Master Configuration Registers 21.8.2 Bus Matrix Slave Configuration Registers 21.8.3 Bus Matrix Priority Registers For Slaves 21.8.4 Bus Matrix Master Remap Control Register 21.8.5 System I/O Configuration Register 21.8.6 Write Protect Mode Register 21.8.7 Write Protect Status Register 22. AHB DMA Controller (DMAC) 22.1 Description 22.2 Embedded Characteristics 22.3 Block Diagram 22.4 Functional Description 22.4.1 Basic Definitions 22.4.2 Memory Peripherals 22.4.3 Handshaking Interface 22.4.3.1 Software Handshaking 22.4.4 DMAC Transfer Types 22.4.4.1 Multi-buffer Transfers 22.4.4.3 Ending Multi-buffer Transfers 22.4.5 Programming a Channel 22.4.5.1 Programming Examples 22.4.6 Disabling a Channel Prior to Transfer Completion 22.4.6.1 Abnormal Transfer Termination 22.5 DMAC Software Requirements 22.6 Write Protection Registers 22.7 AHB DMA Controller (DMAC) User Interface 22.7.1 DMAC Global Configuration Register 22.7.2 DMAC Enable Register 22.7.3 DMAC Software Single Request Register 22.7.4 DMAC Software Chunk Transfer Request Register 22.7.5 DMAC Software Last Transfer Flag Register 22.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register 22.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register 22.7.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register 22.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register 22.7.10 DMAC Channel Handler Enable Register 22.7.11 DMAC Channel Handler Disable Register 22.7.12 DMAC Channel Handler Status Register 22.7.13 DMAC Channel x [x = 0..5] Source Address Register 22.7.14 DMAC Channel x [x = 0..5] Destination Address Register 22.7.15 DMAC Channel x [x = 0..5] Descriptor Address Register 22.7.16 DMAC Channel x [x = 0..5] Control A Register 22.7.17 DMAC Channel x [x = 0..5] Control B Register 22.7.18 DMAC Channel x [x = 0..5] Configuration Register 22.7.19 DMAC Write Protect Mode Register 22.7.20 DMAC Write Protect Status Register 23. External Memory Bus 23.1 Description 23.2 Embedded Characteristics 23.3 Block Diagram 23.4 I/O Lines Description 23.5 Application Example 23.5.1 Hardware Interface 23.6 Product Dependencies 23.6.1 I/O Lines 23.7 Functional Description 23.7.1 Bus Multiplexing 23.7.2 Static Memory Controller 23.7.3 NAND Flash Controller 23.7.4 SDRAM Controller 23.7.5 ECC Controller 23.8 Implementation Examples 23.8.1 SDR-SDRAM 23.8.1.1 Software Configuration (2 x 8-bit SDR-SDRAM) 23.8.1.2 Software Configuration (1 x 16-bit SDR-SDRAM) 23.8.2 8-bit and 16-bit NAND Flash 23.8.2.1 Software Configuration (8-bit and 16-bit NAND Flash) 23.8.3 NOR Flash on NCS0 23.8.3.1 Software Configuration (NOR Flash on NCS0) 24. AHB SDRAM Controller (SDRAMC) 24.1 Description 24.2 Embedded Characteristics 24.3 I/O Lines Description 24.4 Application Example 24.4.1 Software Interface 24.4.1.1 16-bit Memory Data Bus Width 24.5 Product Dependencies 24.5.1 SDRAM Device Initialization 24.5.2 I/O Lines 24.5.3 Interrupt 24.5.4 Power Management 24.7 AHB SDRAM Controller (SDRAMC) User Interface 24.7.1 SDRAMC Mode Register 24.7.2 SDRAMC Refresh Timer Register 24.7.3 SDRAMC Configuration Register 24.7.4 SDRAMC Low Power Register 24.7.5 SDRAMC Interrupt Enable Register 24.7.6 SDRAMC Interrupt Disable Register 24.7.7 SDRAMC Interrupt Mask Register 24.7.8 SDRAMC Interrupt Status Register 24.7.9 SDRAMC Memory Device Register 24.7.10 SDRAMC Configuration 1 Register 24.7.11 SDRAMC OCMS Register 25. Static Memory Controller (SMC) 25.1 Description 25.2 Embedded Characteristics 25.3 Block Diagram 25.4 I/O Lines Description 25.5 Multiplexed Signals 25.6 Application Example 25.6.1 Implementation Examples 25.6.2 Hardware Interface 25.7 Product Dependencies 25.7.1 I/O Lines 25.7.2 Power Management 25.7.3 Interrupt 25.8 External Memory Mapping 25.9 Connection to External Devices 25.9.1 Data Bus Width 25.9.2 Byte Write or Byte Select Access 25.9.2.1 Byte Write Access 25.9.2.2 Byte Select Access 25.9.2.3 Signal Multiplexing 25.10 Standard Read and Write Protocols 25.10.1 Read Waveforms 25.10.1.1 NRD Waveform 25.10.1.2 NCS Waveform 25.10.1.3 Read Cycle 25.10.2 Read Mode 25.10.2.1 Read is Controlled by NRD (READ_MODE = 1): 25.10.2.2 Read is Controlled by NCS (READ_MODE = 0) 25.10.3 Write Waveforms 25.10.3.1 NWE Waveforms 25.10.3.2 NCS Waveforms 25.10.3.3 Write Cycle 25.10.4 Write Mode 25.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1) 25.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0) 25.10.5 Coding Timing Parameters 25.10.6 Reset Values of Timing Parameters 25.10.7 Usage Restriction 25.10.7.1 For Read Operations 25.10.7.2 For Write Operations 25.11 Scrambling/Unscrambling Function 25.12 Automatic Wait States 25.12.1 Chip Select Wait States 25.12.2 Early Read Wait State 25.12.3 Reload User Configuration Wait State 25.12.3.1 User Procedure 25.12.3.2 Slow Clock Mode Transition 25.12.4 Read to Write Wait State 25.13 Data Float Wait States 25.13.1 READ_MODE 25.13.2 TDF Optimization Enabled (TDF_MODE = 1) 25.13.3 TDF Optimization Disabled (TDF_MODE = 0) 25.14 External Wait 25.14.1 Restriction 25.14.2 Frozen Mode 25.14.3 Ready Mode 25.14.4 NWAIT Latency and Read/Write Timings 25.15 Slow Clock Mode 25.15.1 Slow Clock Mode Waveforms 25.15.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 25.16 NAND Flash Controller Operations 25.16.1 NFC Overview 25.16.2 NFC Control Registers 25.16.2.1 Building NFC Address Command Example. 25.16.2.2 NFC Address Command 25.16.2.3 NFC Data Address 25.16.2.4 NFC DATA Status 25.16.3 NFC Initialization 25.16.3.1 NAND Flash Controller Timing Engine 25.16.4 NFC SRAM 25.16.4.1 NFC SRAM Mapping 25.16.4.2 NFC SRAM Access Prioritization Algorithm 25.16.5 NAND Flash Operations 25.16.5.1 Page Read 25.16.5.2 Program Page 25.17 SMC Error Correcting Code Functional Description 25.17.1 Write Access 25.17.2 Read Access 25.18 Static Memory Controller (SMC) User Interface 25.18.1 SMC NFC Configuration Register 25.18.2 SMC NFC Control Register 25.18.3 SMC NFC Status Register 25.18.4 SMC NFC Interrupt Enable Register 25.18.5 SMC NFC Interrupt Disable Register 25.18.6 SMC NFC Interrupt Mask Register 25.18.7 SMC NFC Address Cycle Zero Register 25.18.8 SMC NFC Bank Register 25.18.9 SMC ECC Control Register 25.18.10 SMC ECC MODE Register 25.18.11 SMC ECC Status Register 1 25.18.12 SMC ECC Status Register 2 25.18.13 SMC ECC Parity Register 0 for a Page of 512/1024/2048/4096 Bytes 25.18.14 SMC ECC Parity Register 1 for a Page of 512/1024/2048/4096 Bytes 25.18.15 SMC ECC Parity Registers for 1 ECC per 512 Bytes for a Page of 512/2048/4096 Bytes, 9-bit Word 25.18.16 SMC ECC Parity Registers for 1 ECC per 256 Bytes for a Page of 512/2048/4096 Bytes, 8-bit Word 25.18.17 SMC Setup Register 25.18.18 SMC Pulse Register 25.18.19 SMC Cycle Register 25.18.20 SMC Timings Register 25.18.21 SMC Mode Register 25.18.22 SMC OCMS Register 25.18.23 SMC OCMS Key1 Register 25.18.24 SMC OCMS Key2 Register 25.18.25 SMC Write Protection Control 25.18.26 SMC Write Protection Status 26. Peripheral DMA Controller (PDC) 26.1 Description 26.2 Embedded Characteristics 26.3 Block Diagram 26.4 Functional Description 26.4.1 Configuration 26.4.2 Memory Pointers 26.4.3 Transfer Counters 26.4.4 Data Transfers 26.4.5 PDC Flags and Peripheral Status Register 26.4.5.1 Receive Transfer End 26.4.5.2 Transmit Transfer End 26.4.5.3 Receive Buffer Full 26.4.5.4 Transmit Buffer Empty 26.5 Peripheral DMA Controller (PDC) User Interface 26.5.1 Receive Pointer Register 26.5.2 Receive Counter Register 26.5.3 Transmit Pointer Register 26.5.4 Transmit Counter Register 26.5.5 Receive Next Pointer Register 26.5.6 Receive Next Counter Register 26.5.7 Transmit Next Pointer Register 26.5.8 Transmit Next Counter Register 26.5.9 Transfer Control Register 26.5.10 Transfer Status Register 27. Clock Generator 27.1 Description 27.2 Embedded Characteristics 27.3 Block Diagram 27.4 Slow Clock 27.4.1 Slow Clock RC Oscillator 27.4.2 Slow Clock Crystal Oscillator 27.5 Main Clock 27.5.2 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator 27.5.3 Main Clock Oscillator Selection 28. Power Management Controller (PMC) 28.1 Description 28.2 Embedded Characteristics 28.3 Block Diagram 28.8 Free Running Processor Clock 28.9 Programmable Clock Output Controller 28.10 Fast Startup 28.11 Main Crystal Clock Failure Detector 28.12 Programming Sequence 28.13 Clock Switching Details 28.13.0.1 Master Clock Switching Timings 28.13.0.2 Clock Switching Waveforms 28.14 Write Protection Registers 28.15 Power Management Controller (PMC) User Interface 28.15.1 PMC System Clock Enable Register 28.15.2 PMC System Clock Disable Register 28.15.3 PMC System Clock Status Register 28.15.4 PMC Peripheral Clock Enable Register 0 28.15.5 PMC Peripheral Clock Disable Register 0 28.15.6 PMC Peripheral Clock Status Register 0 28.15.7 PMC UTMI Clock Configuration Register 28.15.8 PMC Clock Generator Main Oscillator Register 28.15.9 PMC Clock Generator Main Clock Frequency Register 28.15.10 PMC Clock Generator PLLA Register 28.15.11 PMC Master Clock Register 28.15.12 PMC USB Clock Register 28.15.13 PMC Programmable Clock Register 28.15.14 PMC Interrupt Enable Register 28.15.15 PMC Interrupt Disable Register 28.15.16 PMC Status Register 28.15.17 PMC Interrupt Mask Register 28.15.18 PMC Fast Startup Mode Register 28.15.19 PMC Fast Startup Polarity Register 28.15.20 PMC Fault Output Clear Register 28.15.21 PMC Write Protect Mode Register 28.15.22 PMC Write Protect Status Register 28.15.23 PMC Peripheral Clock Enable Register 1 28.15.24 PMC Peripheral Clock Disable Register 1 28.15.25 PMC Peripheral Clock Status Register 1 28.15.26 PMC Peripheral Control Register 29. Chip Identifier (CHIPID) 29.1 Description 29.2 Embedded Characteristics 29.3 Chip Identifier (CHIPID) User Interface 29.3.1 Chip ID Register 29.3.2 Chip ID Extension Register 30. Synchronous Serial Controller (SSC) 30.1 Description 30.2 Embedded Characteristics 30.5 Pin Name List 30.6 Product Dependencies 30.6.1 I/O Lines 30.6.2 Power Management 30.6.3 Interrupt 30.7 Functional Description 30.7.1 Clock Management 30.7.1.2 Transmitter Clock Management 30.7.1.3 Receiver Clock Management 30.7.1.4 Serial Clock Ratio Considerations 30.7.7 Data Format 30.7.8 Loop Mode 30.7.9 Interrupt 30.8 SSC Application Examples 30.8.1 Write Protection Registers 30.9 Synchronous Serial Controller (SSC) User Interface 30.9.1 SSC Control Register 30.9.2 SSC Clock Mode Register 30.9.3 SSC Receive Clock Mode Register 30.9.4 SSC Receive Frame Mode Register 30.9.5 SSC Transmit Clock Mode Register 30.9.6 SSC Transmit Frame Mode Register 30.9.7 SSC Receive Holding Register 30.9.8 SSC Transmit Holding Register 30.9.9 SSC Receive Synchronization Holding Register 30.9.10 SSC Transmit Synchronization Holding Register 30.9.11 SSC Receive Compare 0 Register 30.9.12 SSC Receive Compare 1 Register 30.9.13 SSC Status Register 30.9.14 SSC Interrupt Enable Register 30.9.15 SSC Interrupt Disable Register 30.9.16 SSC Interrupt Mask Register 30.9.17 SSC Write Protect Mode Register 30.9.18 SSC Write Protect Status Register 31. Parallel Input/Output Controller (PIO) 31.1 Description 31.2 Embedded Characteristics 31.3 Block Diagram 31.4 Product Dependencies 31.4.1 Pin Multiplexing 31.4.2 Power Management 31.4.3 Interrupt Generation 31.5 Functional Description 31.5.1 Pull-up Resistor Control 31.5.2 I/O Line or Peripheral Function Selection 31.5.3 Peripheral A or B Selection 31.5.4 Output Control 31.5.5 Synchronous Data Output 31.5.6 Multi Drive Control (Open Drain) 31.5.7 Output Line Timings 31.5.8 Inputs 31.5.9 Input Glitch and Debouncing Filters 31.5.10 Input Edge/Level Interrupt 31.5.10.1 Example 31.5.10.2 Interrupt Mode Configuration 31.5.10.3 Edge or Level Detection Configuration 31.5.10.4 Falling/Rising Edge or Low/High Level Detection Configuration. 31.5.11 I/O Lines Lock 31.6 I/O Lines Programming Example 31.6.1 Write Protection Registers 31.7 Parallel Input/Output Controller (PIO) User Interface 31.7.1 PIO Controller PIO Enable Register 31.7.2 PIO Controller PIO Disable Register 31.7.3 PIO Controller PIO Status Register 31.7.4 PIO Controller Output Enable Register 31.7.5 PIO Controller Output Disable Register 31.7.6 PIO Controller Output Status Register 31.7.7 PIO Controller Input Filter Enable Register 31.7.8 PIO Controller Input Filter Disable Register 31.7.9 PIO Controller Input Filter Status Register 31.7.10 PIO Controller Set Output Data Register 31.7.11 PIO Controller Clear Output Data Register 31.7.12 PIO Controller Output Data Status Register 31.7.13 PIO Controller Pin Data Status Register 31.7.14 PIO Controller Interrupt Enable Register 31.7.15 PIO Controller Interrupt Disable Register 31.7.16 PIO Controller Interrupt Mask Register 31.7.17 PIO Controller Interrupt Status Register 31.7.18 PIO Multi-driver Enable Register 31.7.19 PIO Multi-driver Disable Register 31.7.20 PIO Multi-driver Status Register 31.7.21 PIO Pull Up Disable Register 31.7.22 PIO Pull Up Enable Register 31.7.23 PIO Pull Up Status Register 31.7.24 PIO Peripheral AB Select Register 31.7.25 PIO System Clock Glitch Input Filtering Select Register 31.7.26 PIO Debouncing Input Filtering Select Register 31.7.27 PIO Glitch or Debouncing Input Filter Selection Status Register 31.7.28 PIO Slow Clock Divider Debouncing Register 31.7.29 PIO Output Write Enable Register 31.7.30 PIO Output Write Disable Register 31.7.31 PIO Output Write Status Register 31.7.32 Additional Interrupt Modes Enable Register 31.7.33 Additional Interrupt Modes Disable Register 31.7.34 Additional Interrupt Modes Mask Register 31.7.35 Edge Select Register 31.7.36 Level Select Register 31.7.37 Edge/Level Status Register 31.7.38 Falling Edge/Low Level Select Register 31.7.39 Rising Edge/High Level Select Register 31.7.40 Fall/Rise - Low/High Status Register 31.7.41 Lock Status Register 31.7.42 PIO Write Protect Mode Register 31.7.43 PIO Write Protect Status Register 32. Serial Peripheral Interface (SPI) 32.1 Description 32.2 Embedded Characteristics 32.3 Block Diagram 32.4 Application Block Diagram 32.5 Signal Description 32.6 Product Dependencies 32.6.1 I/O Lines 32.6.2 Power Management 32.6.3 Interrupt 32.7 Functional Description 32.7.1 Modes of Operation 32.7.2 Data Transfer 32.7.3 Master Mode Operations 32.7.3.1 Master Mode Block Diagram 32.7.3.2 Master Mode Flow Diagram 32.7.3.3 Clock Generation 32.7.3.4 Transfer Delays 32.7.3.5 Peripheral Selection 32.7.3.6 SPI Direct Access Memory Controller (DMAC) 32.7.3.7 Peripheral Chip Select Decoding 32.7.3.8 Peripheral Deselection without DMAC 32.7.3.9 Peripheral Deselection with DMAC 32.7.3.10 Mode Fault Detection 32.7.4 SPI Slave Mode 32.7.5 Write Protected Registers 32.8 Serial Peripheral Interface (SPI) User Interface 32.8.1 SPI Control Register 32.8.2 SPI Mode Register 32.8.3 SPI Receive Data Register 32.8.4 SPI Transmit Data Register 32.8.5 SPI Status Register 32.8.6 SPI Interrupt Enable Register 32.8.7 SPI Interrupt Disable Register 32.8.8 SPI Interrupt Mask Register 32.8.9 SPI Chip Select Register 32.8.10 SPI Write Protection Mode Register 32.8.11 SPI Write Protection Status Register 33. Two-wire Interface (TWI) 33.1 Description 33.2 Embedded Characteristics 33.3 List of Abbreviations 33.4 Block Diagram 33.5 Application Block Diagram 33.5.1 I/O Lines Description 33.6 Product Dependencies 33.6.1 I/O Lines 33.6.2 Power Management 33.6.3 Interrupt 33.7 Functional Description 33.7.1 Transfer Format 33.7.2 Modes of Operation 33.8 Master Mode 33.8.1 Definition 33.8.2 Application Block Diagram 33.8.3 Programming Master Mode 33.8.4 Master Transmitter Mode 33.8.5 Master Receiver Mode 33.8.6 Internal Address 33.8.6.1 7-bit Slave Addressing 33.8.6.2 10-bit Slave Addressing 33.8.7 Using the Peripheral DMA Controller (PDC) 33.8.7.1 Data Transmit with the PDC 33.8.7.2 Data Receive with the PDC 33.8.8 SMBUS Quick Command (Master Mode Only) 33.8.9 Read-write Flowcharts 33.9 Multi-master Mode 33.9.1 Definition 33.9.2 Different Multi-master Modes 33.9.2.1 TWI as Master Only 33.9.2.2 TWI as Master or Slave 33.10 Slave Mode 33.10.1 Definition 33.10.2 Application Block Diagram 33.10.3 Programming Slave Mode 33.10.4 Receiving Data 33.10.4.1 Read Sequence 33.10.4.2 Write Sequence 33.10.4.3 Clock Synchronization Sequence 33.10.4.4 General Call 33.10.4.5 PDC 33.10.5 Data Transfer 33.10.5.1 Read Operation 33.10.5.2 Write Operation 33.10.5.3 General Call 33.10.5.4 Clock Synchronization 33.10.5.5 Reversal after a Repeated Start 33.10.6 Read Write Flowcharts 33.11 Two-wire Interface (TWI) User Interface 33.11.1 TWI Control Register 33.11.2 TWI Master Mode Register 33.11.3 TWI Slave Mode Register 33.11.4 TWI Internal Address Register 33.11.5 TWI Clock Waveform Generator Register 33.11.6 TWI Status Register 33.11.7 TWI Interrupt Enable Register 33.11.8 TWI Interrupt Disable Register 33.11.9 TWI Interrupt Mask Register 33.11.10 TWI Receive Holding Register 33.11.11 TWI Transmit Holding Register 34. Universal Asynchronous Receiver Transceiver (UART) 34.1 Description 34.2 Embedded Characteristics 34.3 Block Diagram 34.4 Product Dependencies 34.4.1 I/O Lines 34.4.2 Power Management 34.4.3 Interrupt Source 34.5 UART Operations 34.5.1 Baud Rate Generator 34.5.2 Receiver 34.5.2.1 Receiver Reset, Enable and Disable 34.5.2.2 Start Detection and Data Sampling 34.5.2.3 Receiver Ready 34.5.2.4 Receiver Overrun 34.5.2.5 Parity Error 34.5.2.6 Receiver Framing Error 34.5.3 Transmitter 34.5.3.1 Transmitter Reset, Enable and Disable 34.5.3.2 Transmit Format 34.5.3.3 Transmitter Control 34.5.4 Peripheral DMA Controller 34.5.5 Test Modes 34.6 Universal Asynchronous Receiver Transceiver (UART) User Interface 34.6.1 UART Control Register 34.6.2 UART Mode Register 34.6.3 UART Interrupt Enable Register 34.6.4 UART Interrupt Disable Register 34.6.5 UART Interrupt Mask Register 34.6.6 UART Status Register 34.6.7 UART Receiver Holding Register 34.6.8 UART Transmit Holding Register 34.6.9 UART Baud Rate Generator Register 35. Universal Synchronous Asynchronous Receiver Transmitter (USART) 35.1 Description 35.2 Embedded Characteristics 35.3 Block Diagram 35.4 Application Block Diagram 35.5 I/O Lines Description 35.6 Product Dependencies 35.6.1 I/O Lines 35.6.2 Power Management 35.6.3 Interrupt 35.7 Functional Description 35.7.1 Baud Rate Generator 35.7.1.1 Baud Rate in Asynchronous Mode 35.7.1.2 Fractional Baud Rate in Asynchronous Mode 35.7.1.3 Baud Rate in Synchronous Mode or SPI Mode 35.7.1.4 Baud Rate in ISO 7816 Mode 35.7.3 Synchronous and Asynchronous Modes 35.7.3.2 Manchester Encoder 35.7.3.3 Asynchronous Receiver 35.7.3.4 Manchester Decoder 35.7.3.5 Radio Interface: Manchester Encoded USART Application 35.7.3.6 Synchronous Receiver 35.7.3.7 Receiver Operations 35.7.3.8 Parity 35.7.3.9 Multidrop Mode 35.7.3.10 Transmitter Timeguard 35.7.3.11 Receiver Time-out 35.7.3.12 Framing Error 35.7.3.13 Transmit Break 35.7.3.14 Receive Break 35.7.3.15 Hardware Handshaking 35.7.4 ISO7816 Mode 35.7.4.1 ISO7816 Mode Overview 35.7.4.2 Protocol T = 0 35.7.4.3 Protocol T = 1 35.7.5 IrDA Mode 35.7.5.1 IrDA Modulation 35.7.5.2 IrDA Baud Rate 35.7.5.3 IrDA Demodulator 35.7.6 RS485 Mode 35.7.7 SPI Mode 35.7.7.1 Modes of Operation 35.7.7.2 Baud Rate 35.7.7.3 Data Transfer 35.7.7.4 Receiver and Transmitter Control 35.7.7.5 Character Transmission 35.7.7.6 Character Reception 35.7.7.7 Receiver Timeout 35.7.8 LIN Mode 35.7.8.1 Modes of Operation 35.7.8.2 Baud Rate Configuration 35.7.8.3 Receiver and Transmitter Control 35.7.8.4 Character Transmission 35.7.8.5 Character Reception 35.7.8.6 Header Transmission (Master Node Configuration) 35.7.8.7 Header Reception (Slave Node Configuration) 35.7.8.8 Slave Node Synchronization 35.7.8.9 Identifier Parity 35.7.8.10 Node Action 35.7.8.11 Response Data Length 35.7.8.12 Checksum 35.7.8.13 Frame Slot Mode 35.7.8.14 LIN Errors 35.7.8.15 LIN Frame Handling 35.7.8.16 LIN Frame Handling With The PDC 35.7.8.17 Wake-up Request 35.7.8.18 Bus Idle Time-out 35.7.9 Test Modes 35.7.9.1 Normal Mode 35.7.9.2 Automatic Echo Mode 35.7.9.3 Local Loopback Mode 35.7.9.4 Remote Loopback Mode 35.7.10 Write Protection Registers 35.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface 35.8.1 USART Control Register 35.8.2 USART Mode Register 35.8.3 USART Interrupt Enable Register 35.8.4 USART Interrupt Disable Register 35.8.5 USART Interrupt Mask Register 35.8.6 USART Channel Status Register 35.8.7 USART Receive Holding Register 35.8.8 USART Transmit Holding Register 35.8.9 USART Baud Rate Generator Register 35.8.10 USART Receiver Time-out Register 35.8.11 USART Transmitter Timeguard Register 35.8.12 USART FI DI RATIO Register 35.8.13 USART Number of Errors Register 35.8.14 USART IrDA FILTER Register 35.8.15 USART Manchester Configuration Register 35.8.16 USART LIN Mode Register 35.8.17 USART LIN Identifier Register 35.8.18 USART Write Protect Mode Register 35.8.19 USART Write Protect Status Register 36. Timer Counter (TC) 36.1 Description 36.2 Embedded Characteristics 36.3 Block Diagram 36.4 Pin Name List 36.5 Product Dependencies 36.5.1 I/O Lines 36.5.2 Power Management 36.5.3 Interrupt Sources 36.5.4 Fault Output 36.6 Functional Description 36.6.1 Description 36.6.2 32-bit Counter 36.6.3 Clock Selection 36.6.4 Clock Control 36.6.5 Operating Modes 36.6.6 Trigger 36.6.7 Capture Mode 36.6.8 Capture Registers A and B 36.6.9 Trigger Conditions 36.6.10 Waveform Mode 36.6.11 Waveform Selection 36.6.11.1 WAVSEL = 00 36.6.11.2 WAVSEL = 10 36.6.11.3 WAVSEL = 01 36.6.11.4 WAVSEL = 11 36.6.12 External Event/Trigger Conditions 36.6.13 Output Controller 36.6.14 Quadrature Decoder 36.6.14.1 Description 36.6.14.2 Input Pre-processing 36.6.14.3 Direction Status and Change Detection 36.6.14.4 Position and Rotation Measurement 36.6.14.5 Speed Measurement 36.6.15 2-bit Gray Up/Down Counter for Stepper Motor 36.6.16 Fault Mode 36.6.17 Register Write Protection 36.7 Timer Counter (TC) User Interface 36.7.1 TC Channel Control Register 36.7.2 TC Channel Mode Register: Capture Mode 36.7.3 TC Channel Mode Register: Waveform Mode 36.7.4 TC Stepper Motor Mode Register 36.7.5 TC Counter Value Register 36.7.6 TC Register A 36.7.7 TC Register B 36.7.8 TC Register C 36.7.9 TC Status Register 36.7.10 TC Interrupt Enable Register 36.7.11 TC Interrupt Disable Register 36.7.12 TC Interrupt Mask Register 36.7.13 TC Block Control Register 36.7.14 TC Block Mode Register 36.7.15 TC QDEC Interrupt Enable Register 36.7.16 TC QDEC Interrupt Disable Register 36.7.17 TC QDEC Interrupt Mask Register 36.7.18 TC QDEC Interrupt Status Register 36.7.19 TC Fault Mode Register 36.7.20 TC Write Protection Mode Register 37. High Speed MultiMedia Card Interface (HSMCI) 37.1 Description 37.2 Embedded Characteristics 37.3 Block Diagram 37.4 Application Block Diagram 37.5 Pin Name List 37.6 Product Dependencies 37.6.1 I/O Lines 37.6.2 Power Management 37.6.3 Interrupt 37.7 Bus Topology 37.8 High Speed MultiMediaCard Operations 37.8.1 Command - Response Operation 37.8.2 Data Transfer Operation 37.8.3 Read Operation 37.8.4 Write Operation 37.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller 37.8.6 READ_SINGLE_BLOCK Operation using DMA Controller 37.8.6.1 Block Length is Multiple of 4 37.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0) 37.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1) 37.8.7 WRITE_MULTIPLE_BLOCK 37.8.7.1 One Block per Descriptor 37.8.8 READ_MULTIPLE_BLOCK 37.8.8.1 Block Length is a Multiple of 4 37.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0) 37.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1) 37.9 SD/SDIO Card Operation 37.9.1 SDIO Data Transfer Type 37.9.2 SDIO Interrupts 37.10 CE-ATA Operation 37.10.1 Executing an ATA Polling Command 37.10.2 Executing an ATA Interrupt Command 37.10.3 Aborting an ATA Command 37.10.4 CE-ATA Error Recovery 37.11 HSMCI Boot Operation Mode 37.11.1 Boot Procedure, Processor Mode 37.11.2 Boot Procedure DMA Mode 37.12 HSMCI Transfer Done Timings 37.12.1 Definition 37.12.2 Read Access 37.12.3 Write Access 37.13 Write Protection Registers 37.14 High Speed MultiMedia Card Interface (HSMCI) User Interface 37.14.1 HSMCI Control Register 37.14.2 HSMCI Mode Register 37.14.3 HSMCI Data Timeout Register 37.14.4 HSMCI SDCard/SDIO Register 37.14.5 HSMCI Argument Register 37.14.6 HSMCI Command Register 37.14.7 HSMCI Block Register 37.14.8 HSMCI Completion Signal Timeout Register 37.14.9 HSMCI Response Register 37.14.10 HSMCI Receive Data Register 37.14.11 HSMCI Transmit Data Register 37.14.12 HSMCI Status Register 37.14.13 HSMCI Interrupt Enable Register 37.14.14 HSMCI Interrupt Disable Register 37.14.15 HSMCI Interrupt Mask Register 37.14.16 HSMCI DMA Configuration Register 37.14.17 HSMCI Configuration Register 37.14.18 HSMCI Write Protect Mode Register 37.14.19 HSMCI Write Protect Status Register 37.14.20 HSMCI FIFOx Memory Aperture 38. Pulse Width Modulation (PWM) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 I/O Lines Description 38.5 Product Dependencies 38.5.1 I/O Lines 38.5.2 Power Management 38.5.3 Interrupt Sources 38.5.4 Fault Inputs 38.6 Functional Description 38.6.1 PWM Clock Generator 38.6.2 PWM Channel 38.6.2.1 Block Diagram 38.6.2.2 Comparator 38.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor 38.6.2.4 Dead-Time Generator 38.6.2.5 Output Override 38.6.2.6 Fault Protection 38.6.2.7 Synchronous Channels 38.6.3 PWM Comparison Units 38.6.4 PWM Event Lines 38.6.5 PWM Controller Operations 38.6.5.1 Initialization 38.6.5.2 Source Clock Selection Criteria 38.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times 38.6.5.6 Interrupts 38.6.5.7 Write Protect Registers 38.7 Pulse Width Modulation (PWM) User Interface 38.7.1 PWM Clock Register 38.7.2 PWM Enable Register 38.7.3 PWM Disable Register 38.7.4 PWM Status Register 38.7.5 PWM Interrupt Enable Register 1 38.7.6 PWM Interrupt Disable Register 1 38.7.7 PWM Interrupt Mask Register 1 38.7.8 PWM Interrupt Status Register 1 38.7.9 PWM Sync Channels Mode Register 38.7.10 PWM Sync Channels Update Control Register 38.7.11 PWM Sync Channels Update Period Register 38.7.12 PWM Sync Channels Update Period Update Register 38.7.13 PWM Interrupt Enable Register 2 38.7.14 PWM Interrupt Disable Register 2 38.7.15 PWM Interrupt Mask Register 2 38.7.16 PWM Interrupt Status Register 2 38.7.17 PWM Output Override Value Register 38.7.18 PWM Output Selection Register 38.7.19 PWM Output Selection Set Register 38.7.20 PWM Output Selection Clear Register 38.7.21 PWM Output Selection Set Update Register 38.7.22 PWM Output Selection Clear Update Register 38.7.23 PWM Fault Mode Register 38.7.24 PWM Fault Status Register 38.7.25 PWM Fault Clear Register 38.7.26 PWM Fault Protection Value Register 38.7.27 PWM Fault Protection Enable Register 1 38.7.28 PWM Fault Protection Enable Register 2 38.7.29 PWM Event Line x Register 38.7.30 PWM Stepper Motor Mode Register 38.7.31 PWM Write Protect Control Register 38.7.32 PWM Write Protect Status Register 38.7.33 PWM Comparison x Value Register 38.7.34 PWM Comparison x Value Update Register 38.7.35 PWM Comparison x Mode Register 38.7.36 PWM Comparison x Mode Update Register 38.7.37 PWM Channel Mode Register 38.7.38 PWM Channel Duty Cycle Register 38.7.39 PWM Channel Duty Cycle Update Register 38.7.40 PWM Channel Period Register 38.7.41 PWM Channel Period Update Register 38.7.42 PWM Channel Counter Register 38.7.43 PWM Channel Dead Time Register 38.7.44 PWM Channel Dead Time Update Register 39. USB On-The-Go Interface (UOTGHS) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.3.1 Application Block Diagram 39.3.1.1 Device Mode 39.3.1.2 Host and OTG Modes 39.3.2 I/O Lines Description 39.4 Product Dependencies 39.4.1 I/O Lines 39.4.2 Clocks 39.4.3 Interrupts 39.4.4 USB Pipe/Endpoint x FIFO Data Register (USBFIFOxDATA) 39.5 Functional Description 39.5.1 USB General Operation 39.5.1.1 Introduction 39.5.1.2 Power-On and Reset 39.5.1.3 Interrupts 39.5.1.4 MCU Power Modes 39.5.1.5 Speed Control 39.5.1.6 DPRAM Management 39.5.1.7 Pad Suspend 39.5.1.8 Customizing of OTG Timers 39.5.1.9 Plug-In Detection 39.5.1.10 ID Detection 39.5.2 USB Device Operation 39.5.2.1 Introduction 39.5.2.2 Power-On and Reset 39.5.2.3 USB Reset 39.5.2.4 Endpoint Reset 39.5.2.5 Endpoint Activation 39.5.2.6 Address Setup 39.5.2.7 Suspend and Wake-up 39.5.2.8 Detach 39.5.2.9 Remote Wake-up 39.5.2.10 STALL Request 39.5.2.11 Management of Control Endpoints 39.5.2.12 Management of IN Endpoints 39.5.2.13 Management of OUT Endpoints 39.5.2.14 Underflow 39.5.2.15 Overflow 39.5.2.16 HB IsoIn Error 39.5.2.17 HB IsoFlush 39.5.2.18 CRC Error 39.5.2.19 Interrupts 39.5.2.20 Test Modes 39.5.3 USB Host Operation 39.5.3.1 Description of Pipes 39.5.3.2 Power-On and Reset 39.5.3.3 Device Detection 39.5.3.4 USB Reset 39.5.3.5 Pipe Reset 39.5.3.6 Pipe Activation 39.5.3.7 Address Setup 39.5.3.8 Remote Wake-up 39.5.3.9 Management of Control Pipes 39.5.3.10 Management of IN Pipes 39.5.3.11 Management of OUT Pipes 39.5.3.12 CRC Error 39.5.3.13 Interrupts 39.5.4 USB DMA Operation 39.5.5 USB DMA Channel Transfer Descriptor 39.6 USB On-The-Go Interface (UOTGHS) User Interface 39.6.1 USB General Registers 39.6.1.1 General Control Register 39.6.1.2 General Status Register 39.6.1.3 General Status Clear Register 39.6.1.4 General Status Set Register 39.6.1.5 General Finite State Machine Register 39.6.2 USB Device Registers 39.6.2.1 Device General Control Register 39.6.2.2 Device Global Interrupt Status Register 39.6.2.3 Device Global Interrupt Clear Register 39.6.2.4 Device Global Interrupt Set Register 39.6.2.5 Device Global Interrupt Mask Register 39.6.2.6 Device Global Interrupt Disable Register 39.6.2.7 Device Global Interrupt Enable Register 39.6.2.8 Device Endpoint Register 39.6.2.9 Device Frame Number Register 39.6.2.10 Device Endpoint x Configuration Register 39.6.2.11 Device Endpoint x Status Register 39.6.2.12 Device Endpoint x Clear Register 39.6.2.13 Device Endpoint x Set Register 39.6.2.14 Device Endpoint x Mask Register 39.6.2.15 Device Endpoint x Disable Register 39.6.2.16 Device Endpoint x Enable Register 39.6.2.17 Device DMA Channel x Next Descriptor Address Register 39.6.2.18 Device DMA Channel x Address Register 39.6.2.19 Device DMA Channel x Control Register 39.6.2.20 Device DMA Channel x Status Register 39.6.3 USB Host Registers 39.6.3.1 Host General Control Register 39.6.3.2 Host Global Interrupt Status Register 39.6.3.3 Host Global Interrupt Clear Register 39.6.3.4 Host Global Interrupt Set Register 39.6.3.5 Host Global Interrupt Mask Register 39.6.3.6 Host Global Interrupt Disable Register 39.6.3.7 Host Global Interrupt Enable Register 39.6.3.8 Host Frame Number Register 39.6.3.9 Host Address 1 Register 39.6.3.10 Host Address 2 Register 39.6.3.11 Host Address 3 Register 39.6.3.12 Host Pipe Register 39.6.3.13 Host Pipe x Configuration Register 39.6.3.14 Host Pipe x Status Register 39.6.3.15 Host Pipe x Clear Register 39.6.3.16 Host Pipe x Set Register 39.6.3.17 Host Pipe x Mask Register 39.6.3.18 Host Pipe x Disable Register 39.6.3.19 Host Pipe x Enable Register 39.6.3.20 Host Pipe x IN Request Register 39.6.3.21 Host Pipe x Error Register 39.6.3.22 Host DMA Channel x Next Descriptor Address Register 39.6.3.23 Host DMA Channel x Address Register 39.6.3.24 Host DMA Channel x Control Register 39.6.3.25 Host DMA Channel x Status Register 40. Controller Area Network (CAN) 40.1 Description 40.2 Embedded Characteristics 40.3 Block Diagram 40.4 Application Block Diagram 40.5 I/O Lines Description 40.6 Product Dependencies 40.6.1 I/O Lines 40.6.2 Power Management 40.6.3 Interrupt 40.7 CAN Controller Features 40.7.1 CAN Protocol Overview 40.7.2 Mailbox Organization 40.7.2.1 Message Acceptance Procedure 40.7.2.2 Receive Mailbox 40.7.2.3 Transmit Mailbox 40.7.3 Time Management Unit 40.7.4 CAN 2.0 Standard Features 40.7.4.1 CAN Bit Timing Configuration 40.7.4.2 Error Detection 40.7.4.3 Overload 40.7.5 Low-power Mode 40.7.5.1 Enabling Low-power Mode 40.7.5.2 Disabling Low-power Mode 40.8 Functional Description 40.8.1 CAN Controller Initialization 40.8.2 CAN Controller Interrupt Handling 40.8.3 CAN Controller Message Handling 40.8.3.1 Receive Handling 40.8.3.2 Transmission Handling 40.8.3.3 Remote Frame Handling 40.8.4 CAN Controller Timing Modes 40.8.4.1 Timestamping Mode 40.8.4.2 Time Triggered Mode 40.8.5 Write Protected Registers 40.9 Controller Area Network (CAN) User Interface 40.9.1 CAN Mode Register 40.9.2 CAN Interrupt Enable Register 40.9.3 CAN Interrupt Disable Register 40.9.4 CAN Interrupt Mask Register 40.9.5 CAN Status Register 40.9.6 CAN Baudrate Register 40.9.7 CAN Timer Register 40.9.8 CAN Timestamp Register 40.9.9 CAN Error Counter Register 40.9.10 CAN Transfer Command Register 40.9.11 CAN Abort Command Register 40.9.12 CAN Write Protection Mode Register 40.9.13 CAN Write Protection Status Register 40.9.14 CAN Message Mode Register 40.9.15 CAN Message Acceptance Mask Register 40.9.16 CAN Message ID Register 40.9.17 CAN Message Family ID Register 40.9.18 CAN Message Status Register 40.9.19 CAN Message Data Low Register 40.9.20 CAN Message Data High Register 40.9.21 CAN Message Control Register 41. Ethernet MAC 10/100 (EMAC) 41.1 Description 41.2 Embedded Characteristics 41.4 Functional Description 41.4.1 Clock 41.4.2 Memory Interface 41.4.2.1 FIFO 41.4.2.2 Receive Buffers 41.4.2.3 Transmit Buffer 41.4.3 Transmit Block 41.4.4 Pause Frame Support 41.4.5 Receive Block 41.4.6 Address Checking Block 41.4.7 Broadcast Address 41.4.8 Hash Addressing 41.4.9 Copy All Frames (or Promiscuous Mode) 41.4.10 Type ID Checking 41.4.11 VLAN Support 41.4.12 PHY Maintenance 41.4.13 Physical Interface 41.4.13.1 RMII Transmit and Receive Operation 41.5 Programming Interface 41.5.1 Initialization 41.5.1.3 Transmit Buffer List 41.5.1.4 Address Matching 41.5.1.5 Interrupts 41.5.1.6 Transmitting Frames 41.5.1.7 Receiving Frames 41.6 Ethernet MAC 10/100 (EMAC) User Interface 41.6.1 Network Control Register 41.6.2 Network Configuration Register 41.6.3 Network Status Register 41.6.4 Transmit Status Register 41.6.5 Receive Buffer Queue Pointer Register 41.6.6 Transmit Buffer Queue Pointer Register 41.6.7 Receive Status Register 41.6.8 Interrupt Status Register 41.6.9 Interrupt Enable Register 41.6.10 Interrupt Disable Register 41.6.11 Interrupt Mask Register 41.6.12 PHY Maintenance Register 41.6.13 Pause Time Register 41.6.14 Hash Register Bottom 41.6.15 Hash Register Top 41.6.16 Specific Address 1 Bottom Register 41.6.17 Specific Address 1 Top Register 41.6.18 Specific Address 2 Bottom Register 41.6.19 Specific Address 2 Top Register 41.6.20 Specific Address 3 Bottom Register 41.6.21 Specific Address 3 Top Register 41.6.22 Specific Address 4 Bottom Register 41.6.23 Specific Address 4 Top Register 41.6.24 Type ID Checking Register 41.6.25 User Input/Output Register 41.6.26 EMAC Statistic Registers 41.6.26.1 Pause Frames Received Register 41.6.26.2 Frames Transmitted OK Register 41.6.26.3 Single Collision Frames Register 41.6.26.4 Multicollision Frames Register 41.6.26.5 Frames Received OK Register 41.6.26.6 Frames Check Sequence Errors Register 41.6.26.7 Alignment Errors Register 41.6.26.8 Deferred Transmission Frames Register 41.6.26.9 Late Collisions Register 41.6.26.10 Excessive Collisions Register 41.6.26.11 Transmit Underrun Errors Register 41.6.26.12 Carrier Sense Errors Register 41.6.26.13 Receive Resource Errors Register 41.6.26.14 Receive Overrun Errors Register 41.6.26.15 Receive Symbol Errors Register 41.6.26.16 Excessive Length Errors Register 41.6.26.17 Receive Jabbers Register 41.6.26.18 Undersize Frames Register 41.6.26.19 SQE Test Errors Register 41.6.26.20 Received Length Field Mismatch Register 42. True Random Number Generator (TRNG) 42.1 Description 42.2 Embedded Characteristics 42.3 True Random Number Generator (TRNG) User Interface 42.3.1 TRNG Control Register 42.3.2 TRNG Interrupt Enable Register 42.3.3 TRNG Interrupt Disable Register 42.3.4 TRNG Interrupt Mask Register 42.3.5 TRNG Interrupt Status Register 42.3.6 TRNG Output Data Register 43. Analog-to-Digital Converter (ADC) 43.1 Description 43.2 Embedded Characteristics 43.3 Block Diagram 43.4 Signal Description 43.5 Product Dependencies 43.5.1 Power Management 43.5.2 Interrupt Sources 43.5.3 Analog Inputs 43.5.4 Temperature Sensor 43.5.5 I/O Lines 43.5.6 Timer Triggers 43.5.7 PWM Event Line 43.5.8 Fault Output 43.5.9 Conversion Performances 43.6 Functional Description 43.6.1 Analog-to-digital Conversion 43.6.2 Conversion Reference 43.6.3 Conversion Resolution 43.6.4 Conversion Results 43.6.5 Conversion Triggers 43.6.6 Sleep Mode and Conversion Sequencer 43.6.7 Comparison Window 43.6.8 Differential Inputs 43.6.9 Input Gain and Offset 43.6.10 ADC Timings 43.6.11 Buffer Structure 43.6.12 Fault Output 43.6.13 Write Protection Registers 43.7 Analog-to-Digital Converter (ADC) User Interface 43.7.1 ADC Control Register 43.7.2 ADC Mode Register 43.7.3 ADC Channel Sequence 1 Register 43.7.4 ADC Channel Sequence 2 Register 43.7.5 ADC Channel Enable Register 43.7.6 ADC Channel Disable Register 43.7.7 ADC Channel Status Register 43.7.8 ADC Last Converted Data Register 43.7.9 ADC Interrupt Enable Register 43.7.10 ADC Interrupt Disable Register 43.7.11 ADC Interrupt Mask Register 43.7.12 ADC Interrupt Status Register 43.7.13 ADC Overrun Status Register 43.7.14 ADC Extended Mode Register 43.7.15 ADC Compare Window Register 43.7.16 ADC Channel Gain Register 43.7.17 ADC Channel Offset Register 43.7.18 ADC Channel Data Register 43.7.19 ADC Analog Control Register 43.7.20 ADC Write Protect Mode Register 43.7.21 ADC Write Protect Status Register 44. Digital-to-Analog Converter Controller (DACC) 44.1 Description 44.2 Embedded Characteristics 44.3 Block Diagram 44.4 Signal Description 44.5 Product Dependencies 44.5.1 Power Management 44.5.2 Interrupt Sources 44.5.3 Conversion Performances 44.6 Functional Description 44.6.1 Digital-to-Analog Conversion 44.6.2 Conversion Results 44.6.3 Conversion Triggers 44.6.4 Conversion FIFO 44.6.5 Channel Selection 44.6.6 Sleep Mode 44.6.7 DACC Timings 44.6.8 Write Protection Registers 44.7 Analog Converter Controller (DACC) User Interface 44.7.1 DACC Control Register 44.7.2 DACC Mode Register 44.7.3 DACC Channel Enable Register 44.7.4 DACC Channel Disable Register 44.7.5 DACC Channel Status Register 44.7.6 DACC Conversion Data Register 44.7.7 DACC Interrupt Enable Register 44.7.8 DACC Interrupt Disable Register 44.7.9 DACC Interrupt Mask Register 44.7.10 DACC Interrupt Status Register 44.7.11 DACC Analog Current Register 44.7.12 DACC Write Protect Mode Register 44.7.13 DACC Write Protect Status Register 45. Electrical Characteristics 45.1 Absolute Maximum Ratings 45.2 DC Characteristics 45.3 Power Consumption 45.3.1 Backup Mode Current Consumption 45.3.1.1 Backup Power Configuration 45.3.2 Wait and Sleep Mode Current Consumption 45.3.2.1 Sleep Mode 45.3.2.2 Wait Mode 45.3.3 Active Mode Power Consumption 45.3.4 Peripheral Power Consumption in Active Mode 45.4 Crystal Oscillators Characteristics 45.4.1 32 kHz RC Oscillator Characteristics 45.4.2 4/8/12 MHz RC Oscillators Characteristics 45.4.3 32.768 kHz Crystal Oscillator Characteristics 45.4.4 32.768 kHz Crystal Characteristics 45.4.5 32.768 kHz XIN32 Clock Input Characteristics in Bypass Mode 45.4.6 3 to 20 MHz Crystal Oscillator Characteristics 45.4.7 3 to 20 MHz Crystal Characteristics 45.4.8 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode 45.4.9 Crystal Oscillator Design Consideration Information 45.4.9.1 Choosing a Crystal 45.4.9.2 Printed Circuit Board (PCB) 45.5 UPLL, PLLA Characteristics 45.6 USB On-the-Go High Speed Port 45.6.1 Typical Connection 45.6.2 Electrical Characteristics 45.6.2.1 USB Transceiver 45.6.2.2 VBUS Pin Characteristics 45.6.3 Static Power Consumption 45.6.4 Dynamic Power Consumption 45.7 12-bit ADC Characteristics 45.7.1 Static Performance Characteristics 45.7.2 Dynamic Performance Characteristics 45.7.2.1 Track and Hold Time versus Source Output Impedance 45.7.3 ADC Application Information 45.8 Temperature Sensor 45.9 12-bit DAC Characteristics 45.10 AC Characteristics 45.10.1 Master Clock Characteristics 45.10.2 I/O Characteristics 45.10.3 SPI Characteristics 45.10.3.1 Maximum SPI Frequency Master Write Mode Master Read Mode Slave Read Mode Slave Write Mode 45.10.3.2 SPI Timings 45.10.4 MCI Timings 45.10.5 SSC Timings 45.10.6 SMC Timings 45.10.6.1 Read Timings 45.10.6.2 Write Timings 45.10.7 USART in SPI Mode Timings 45.10.8 EMAC 45.10.8.1 MII Mode 45.10.8.2 RMII Mode 45.10.9 Two-wire Serial Interface Characteristics 45.10.10 Embedded Flash Characteristics 46. Mechanical Characteristics 46.1 Soldering Profile 46.2 Packaging Resources 47. Marking 48. Ordering Information 49. SAM3X/A Series Errata 49.1 Errata Revision A Parts 49.1.1 Flash Memory 49.1.1.1 Flash: Flash Programming 49.1.1.2 Flash: Fetching Error after Reading the Unique Identifier 49.1.1.3 Flash: Boot Flash Programming Mapping Is Wrong 49.1.1.4 Flash: Flash Programming 49.1.2 Backup Mode 49.1.2.1 Backup mode: The PIO States Are Not Kept 49.1.2.2 Backup Mode: VDDIO/VDDANA 49.1.2.3 Backup Mode Power-Up Sequence 49.1.3 Pulse Width Modulation (PWM) 49.1.3.1 PWM: Write Protection with PIO Lock Feature Not Usable 49.1.4 Analog to Digital Converter (ADC) 49.1.4.1 ADC: First Conversion After Sleep 49.1.4.2 ADC: Last Conversion Error 49.1.4.3 ADC: Wrong First Conversions 49.1.5 JTAG Boundary 49.1.5.1 JJTAG Boundary: PC0/ERASE 50. Revision History Table of Contents

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