Datasheet SAM4E (Microchip) - 3

Cryptography ̶ AES 256-bit Key Algorithm compliant with FIPS Publication 197 Analog ̶ AFE (Analog Front End): 2x16-bit ADC, up to 24-channels, Differential Input Mode, Programmable Gain Stage, Auto Calibration and Automatic Offset Correction ̶ One 2-channel 12-bit 1 Msps DAC ̶ One Analog Comparator with Flexible Input Selection, Selectable Input Hysteresis I/O ̶ Up to 117 I/O Lines with External Interrupt Capability (Edge or Level Sensitivity), Debouncing, Glitch Filtering and On-die Series Resistor Termination ̶ Bidirectional Pad, Analog I/O, Programmable Pull-up/Pull-down ̶ Five 32-bit Parallel Input/Output Controllers, Peripheral DMA Assisted Parallel Capture Mode Packages ̶ 144-ball LFBGA, 10x10 mm, pitch 0.8 mm ̶ 100-ball TFBGA, 9x9 mm, pitch 0.8 mm ̶ 144-lead LQFP, 20x20 mm, pitch 0.5 mm ̶ 100-lead LQFP, 14x14 mm, pitch 0.5 mm Note: 1. 120 MHz: -40/+105°C, VDDCORE = 1.2V SAM4E Series [DATASHEET] 3 Atmel-11157H-ATARM-SAM4E16-SAM4E8-Datasheet_31-Mar-16 Document Outline Description 1. Features 1.1 Configuration Summary 2. Block Diagram 3. Signal Description 4. Package and Pinout 4.1 100-ball TFBGA Package and Pinout 4.1.1 100-ball TFBGA Package Outline 4.1.2 100-ball TFBGA Pinout 4.2 144-ball LFBGA Package and Pinout 4.2.1 144-ball LFBGA Package Outline 4.2.2 144-ball LFBGA Pinout 4.3 100-lead LQFP Package and Pinout 4.3.1 100-lead LQFP Package Outline 4.3.2 100-lead LQFP Pinout 4.4 144-lead LQFP Package and Pinout 4.4.1 144-lead LQFP Package Outline 4.4.2 144-lead LQFP Pinout 5. Power Considerations 5.1 Power Supplies 5.2 Power-up Considerations 5.2.1 VDDIO Versus VDDCORE 5.2.2 VDDIO Versus VDDIN 5.3 Voltage Regulator 5.4 Typical Powering Schematics 5.6 Low-power Modes 5.6.1 Backup Mode 5.6.2 Wait Mode 5.6.3 Sleep Mode 5.6.4 Low-power Mode Summary Table 5.7 Wake-up Sources 5.8 Fast Start-up 6. Input/Output Lines 6.1 General Purpose I/O Lines 6.2 System I/O Lines 7. Memories 7.1 Product Mapping 7.2 Embedded Memories 7.2.1 Internal SRAM 7.2.2 Internal ROM 7.2.3 Embedded Flash 7.2.3.1 Flash Overview 7.2.3.2 Enhanced Embedded Flash Controller 7.2.3.3 Flash Speed 7.2.3.4 Lock Regions 7.2.3.5 Security Bit Feature 7.2.3.6 Calibration Bits 7.2.3.7 Unique Identifier 7.2.3.8 User Signature 7.2.3.9 Fast Flash Programming Interface 7.2.3.10 SAM-BA Boot 7.2.3.11 GPNVM Bits 7.2.4 Boot Strategies 7.3 External Memories 7.4 Cortex-M Cache Controller (CMCC) 8. Real-time Event Management 8.1 Embedded Characteristics 8.2 Real-time Event Mapping 9. System Controller 9.1 System Controller and Peripherals Mapping 9.2 Power-on-Reset, Brownout and Supply Monitor 9.2.1 Power-on-Reset 9.2.2 Brownout Detector on VDDCORE 9.2.3 Supply Monitor on VDDIO 10. Peripherals 10.1 Peripheral Identifiers 10.2 Peripheral Signal Multiplexing on I/O Lines 10.2.1 PIO Controller A Multiplexing 10.2.2 PIO Controller B Multiplexing 10.2.3 PIO Controller C Multiplexing 10.2.4 PIO Controller D Multiplexing 10.2.5 PIO Controller E Multiplexing 11. Cortex-M4 processor 11.1 Description 11.1.1 System Level Interface 11.1.2 Integrated Configurable Debug 11.2 Embedded Characteristics 11.3 Block Diagram 11.4 Cortex-M4 Models 11.4.1 Programmers Model 11.4.1.1 Processor Modes and Privilege Levels for Software Execution 11.4.1.2 Stacks 11.4.1.3 Core Registers 11.4.1.4 General-purpose Registers 11.4.1.5 Stack Pointer 11.4.1.6 Link Register 11.4.1.7 Program Counter 11.4.1.8 Program Status Register 11.4.1.9 Application Program Status Register 11.4.1.10 Interrupt Program Status Register 11.4.1.11 Execution Program Status Register 11.4.1.12 Exception Mask Registers 11.4.1.13 Priority Mask Register 11.4.1.14 Fault Mask Register 11.4.1.15 Base Priority Mask Register 11.4.1.16 Control Register 11.4.1.17 Exceptions and Interrupts 11.4.1.18 Data Types 11.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS) 11.4.2 Memory Model 11.4.2.1 Memory Regions, Types and Attributes Memory Types Additional Memory Attributes 11.4.2.2 Memory System Ordering of Memory Accesses 11.4.2.3 Behavior of Memory Accesses Additional Memory Access Constraints For Caches and Shared Memory Instruction Prefetch and Branch Prediction 11.4.2.4 Software Ordering of Memory Accesses DMB DSB ISB MPU Programming 11.4.2.5 Bit-banding Directly Accessing an Alias Region Directly Accessing a Bit-band Region 11.4.2.6 Memory Endianness Little-endian Format 11.4.2.7 Synchronization Primitives 11.4.2.8 Programming Hints for the Synchronization Primitives 11.4.3 Exception Model 11.4.3.1 Exception States Inactive Pending Active Active and Pending 11.4.3.2 Exception Types Reset Non Maskable Interrupt (NMI) Hard Fault Memory Management Fault (MemManage) Bus Fault Usage Fault SVCall PendSV SysTick Interrupt (IRQ) 11.4.3.3 Exception Handlers 11.4.3.4 Vector Table 11.4.3.5 Exception Priorities 11.4.3.6 Interrupt Priority Grouping 11.4.3.7 Exception Entry and Return Preemption Return Tail-chaining Late-arriving Exception Entry Exception Return 11.4.3.8 Fault Handling Fault Types Fault Escalation and Hard Faults Fault Status Registers and Fault Address Registers Lockup 11.5 Power Management 11.5.1 Entering Sleep Mode 11.5.1.1 Wait for Interrupt 11.5.1.2 Wait for Event 11.5.1.3 Sleep-on-exit 11.5.2 Wakeup from Sleep Mode 11.5.2.1 Wakeup from WFI or Sleep-on-exit 11.5.2.2 Wakeup from WFE 11.5.2.3 External Event Input 11.5.3 Power Management Programming Hints 11.6 Cortex-M4 Instruction Set 11.6.1 Instruction Set Summary 11.6.2 CMSIS Functions 11.6.3 Instruction Descriptions 11.6.3.1 Operands 11.6.3.2 Restrictions when Using PC or SP 11.6.3.3 Flexible Second Operand Constant Instruction Substitution Register with Optional Shift 11.6.3.4 Shift Operations ASR LSR LSL ROR RRX 11.6.3.5 Address Alignment 11.6.3.6 PC-relative Expressions 11.6.3.7 Conditional Execution Condition Flags Condition Code Suffixes Absolute Value Compare and Update Value 11.6.3.8 Instruction Width Selection 11.6.4 Memory Access Instructions 11.6.4.1 ADR 11.6.4.2 LDR and STR, Immediate Offset 11.6.4.3 LDR and STR, Register Offset 11.6.4.4 LDR and STR, Unprivileged 11.6.4.5 LDR, PC-relative 11.6.4.6 LDM and STM 11.6.4.7 PUSH and POP 11.6.4.8 LDREX and STREX 11.6.4.9 CLREX 11.6.5 General Data Processing Instructions 11.6.5.1 ADD, ADC, SUB, SBC, and RSB 11.6.5.2 AND, ORR, EOR, BIC, and ORN 11.6.5.3 ASR, LSL, LSR, ROR, and RRX 11.6.5.4 CLZ 11.6.5.5 CMP and CMN 11.6.5.6 MOV and MVN 11.6.5.7 MOVT 11.6.5.8 REV, REV16, REVSH, and RBIT 11.6.5.9 SADD16 and SADD8 11.6.5.10 SHADD16 and SHADD8 11.6.5.11 SHASX and SHSAX 11.6.5.12 SHSUB16 and SHSUB8 11.6.5.13 SSUB16 and SSUB8 11.6.5.14 SASX and SSAX 11.6.5.15 TST and TEQ 11.6.5.16 UADD16 and UADD8 11.6.5.17 UASX and USAX 11.6.5.18 UHADD16 and UHADD8 11.6.5.19 UHASX and UHSAX 11.6.5.20 UHSUB16 and UHSUB8 11.6.5.21 SEL 11.6.5.22 USAD8 11.6.5.23 USADA8 11.6.5.24 USUB16 and USUB8 11.6.6 Multiply and Divide Instructions 11.6.6.1 MUL, MLA, and MLS 11.6.6.2 UMULL, UMAAL, UMLAL 11.6.6.3 SMLA and SMLAW 11.6.6.4 SMLAD 11.6.6.5 SMLAL and SMLALD 11.6.6.6 SMLSD and SMLSLD 11.6.6.7 SMMLA and SMMLS 11.6.6.8 SMMUL 11.6.6.9 SMUAD and SMUSD 11.6.6.10 SMUL and SMULW 11.6.6.11 UMULL, UMLAL, SMULL, and SMLAL 11.6.6.12 SDIV and UDIV 11.6.7 Saturating Instructions 11.6.7.1 SSAT and USAT 11.6.7.2 SSAT16 and USAT16 11.6.7.3 QADD and QSUB 11.6.7.4 QASX and QSAX 11.6.7.5 QDADD and QDSUB 11.6.7.6 UQASX and UQSAX 11.6.7.7 UQADD and UQSUB 11.6.8 Packing and Unpacking Instructions 11.6.8.1 PKHBT and PKHTB 11.6.8.2 SXT and UXT 11.6.8.3 SXTA and UXTA 11.6.9 Bitfield Instructions 11.6.9.1 BFC and BFI 11.6.9.2 SBFX and UBFX 11.6.9.3 SXT and UXT 11.6.10 Branch and Control Instructions 11.6.10.1 B, BL, BX, and BLX 11.6.10.2 CBZ and CBNZ 11.6.10.3 IT 11.6.10.4 TBB and TBH 11.6.11 Floating-point Instructions 11.6.11.1 VABS 11.6.11.2 VADD 11.6.11.3 VCMP, VCMPE 11.6.11.4 VCVT, VCVTR between Floating-point and Integer 11.6.11.5 VCVT between Floating-point and Fixed-point 11.6.11.6 VCVTB, VCVTT 11.6.11.7 VDIV 11.6.11.8 VFMA, VFMS 11.6.11.9 VFNMA, VFNMS 11.6.11.10 VLDM 11.6.11.11 VLDR 11.6.11.12 VLMA, VLMS 11.6.11.13 VMOV Immediate 11.6.11.14 VMOV Register 11.6.11.15 VMOV Scalar to ARM Core Register 11.6.11.16 VMOV ARM Core Register to Single Precision 11.6.11.17 VMOV Two ARM Core Registers to Two Single Precision 11.6.11.18 VMOV ARM Core Register to Scalar 11.6.11.19 VMRS 11.6.11.20 VMSR 11.6.11.21 VMUL 11.6.11.22 VNEG 11.6.11.23 VNMLA, VNMLS, VNMUL 11.6.11.24 VPOP 11.6.11.25 VPUSH 11.6.11.26 VSQRT 11.6.11.27 VSTM 11.6.11.28 VSTR 11.6.11.29 VSUB 11.6.12 Miscellaneous Instructions 11.6.12.1 BKPT 11.6.12.2 CPS 11.6.12.3 DMB 11.6.12.4 DSB 11.6.12.5 ISB 11.6.12.6 MRS 11.6.12.7 MSR 11.6.12.8 NOP 11.6.12.9 SEV 11.6.12.10 SVC 11.6.12.11 WFE 11.6.12.12 WFI 11.7 Cortex-M4 Core Peripherals 11.7.1 Peripherals 11.7.2 Address Map 11.8 Nested Vectored Interrupt Controller (NVIC) 11.8.1 Level-sensitive Interrupts 11.8.1.1 Hardware and Software Control of Interrupts 11.8.2 NVIC Design Hints and Tips 11.8.2.1 NVIC Programming Hints 11.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface 11.8.3.1 Interrupt Set-enable Registers 11.8.3.2 Interrupt Clear-enable Registers 11.8.3.3 Interrupt Set-pending Registers 11.8.3.4 Interrupt Clear-pending Registers 11.8.3.5 Interrupt Active Bit Registers 11.8.3.6 Interrupt Priority Registers 11.8.3.7 Software Trigger Interrupt Register 11.9 System Control Block (SCB) 11.9.1 System Control Block (SCB) User Interface 11.9.1.1 Auxiliary Control Register 11.9.1.2 CPUID Base Register 11.9.1.3 Interrupt Control and State Register 11.9.1.4 Vector Table Offset Register 11.9.1.5 Application Interrupt and Reset Control Register 11.9.1.6 System Control Register 11.9.1.7 Configuration and Control Register 11.9.1.8 System Handler Priority Registers 11.9.1.9 System Handler Priority Register 1 11.9.1.10 System Handler Priority Register 2 11.9.1.11 System Handler Priority Register 3 11.9.1.12 System Handler Control and State Register 11.9.1.13 Configurable Fault Status Register 11.9.1.14 Configurable Fault Status Register (Byte Access) 11.9.1.15 Hard Fault Status Register 11.9.1.16 MemManage Fault Address Register 11.9.1.17 Bus Fault Address Register 11.10 System Timer (SysTick) 11.10.1 System Timer (SysTick) User Interface 11.10.1.1 SysTick Control and Status Register 11.10.1.2 SysTick Reload Value Registers 11.10.1.3 SysTick Current Value Register 11.10.1.4 SysTick Calibration Value Register 11.11 Memory Protection Unit (MPU) 11.11.1 MPU Access Permission Attributes 11.11.1.1 MPU Mismatch 11.11.1.2 Updating an MPU Region 11.11.1.3 Updating an MPU Region Using Separate Words 11.11.1.4 Updating an MPU Region Using Multi-word Writes 11.11.1.5 Subregions 11.11.1.6 Example of SRD Use 11.11.1.7 MPU Design Hints And Tips MPU Configuration for a Microcontroller 11.11.2 Memory Protection Unit (MPU) User Interface 11.11.2.1 MPU Type Register 11.11.2.2 MPU Control Register 11.11.2.3 MPU Region Number Register 11.11.2.4 MPU Region Base Address Register 11.11.2.5 MPU Region Attribute and Size Register 11.11.2.6 MPU Region Base Address Register Alias 1 11.11.2.7 MPU Region Attribute and Size Register Alias 1 11.11.2.8 MPU Region Base Address Register Alias 2 11.11.2.9 MPU Region Attribute and Size Register Alias 2 11.11.2.10 MPU Region Base Address Register Alias 3 11.11.2.11 MPU Region Attribute and Size Register Alias 3 11.12 Floating Point Unit (FPU) 11.12.1 Enabling the FPU 11.12.2 Floating Point Unit (FPU) User Interface 11.12.2.1 Coprocessor Access Control Register 11.12.2.2 Floating-point Context Control Register 11.12.2.3 Floating-point Context Address Register 11.12.2.4 Floating-point Status Control Register 11.12.2.5 Floating-point Default Status Control Register 11.13 Glossary 12. Debug and Test Features 12.1 Description 12.2 Embedded Characteristics 12.3 Debug and Test Block Diagram 12.4 Application Examples 12.4.1 Debug Environment 12.4.2 Test Environment 12.5 Debug and Test Pin Description 12.6 Functional Description 12.6.1 Test Pin 12.6.2 NRST Pin 12.6.3 ERASE Pin 12.6.4 Debug Architecture 12.6.5 Serial Wire JTAG Debug Port (SWJ-DP) Pins 12.6.5.1 SW-DP and JTAG-DP Selection Mechanism 12.6.6 FPB (Flash Patch Breakpoint) 12.6.7 DWT (Data Watchpoint and Trace) 12.6.8 ITM (Instrumentation Trace Macrocell) 12.6.8.1 How to Configure the ITM 12.6.8.2 Asynchronous Mode 12.6.8.3 How to Configure the TPIU 12.6.9 IEEE® 1149.1 JTAG Boundary Scan 12.6.9.1 JTAG Boundary-scan Register 12.6.10 ID Code Register 13. Reset Controller (RSTC) 13.1 Description 13.2 Embedded Characteristics 13.3 Block Diagram 13.4 Functional Description 13.4.1 Reset Controller Overview 13.4.2 NRST Manager 13.4.2.1 NRST Signal or Interrupt 13.4.2.2 NRST External Reset Control 13.4.3 Reset States 13.4.3.1 General Reset 13.4.3.2 Backup Reset 13.4.3.3 Watchdog Reset 13.4.3.4 Software Reset 13.4.3.5 User Reset 13.4.4 Reset State Priorities 13.5 Reset Controller (RSTC) User Interface 13.5.1 Reset Controller Control Register 13.5.2 Reset Controller Status Register 13.5.3 Reset Controller Mode Register 14. Real-time Timer (RTT) 14.1 Description 14.2 Embedded Characteristics 14.3 Block Diagram 14.4 Functional Description 14.5 Real-time Timer (RTT) User Interface 14.5.1 Real-time Timer Mode Register 14.5.2 Real-time Timer Alarm Register 14.5.3 Real-time Timer Value Register 14.5.4 Real-time Timer Status Register 15. Real-time Clock (RTC) 15.1 Description 15.2 Embedded Characteristics 15.3 Block Diagram 15.4 Product Dependencies 15.4.1 Power Management 15.4.2 Interrupt 15.5 Functional Description 15.5.1 Reference Clock 15.5.2 Timing 15.5.3 Alarm 15.5.4 Error Checking when Programming 15.5.5 RTC Internal Free Running Counter Error Checking 15.5.6 Updating Time/Calendar 15.5.7 RTC Accurate Clock Calibration 15.5.8 Waveform Generation 15.6 Real-time Clock (RTC) User Interface 15.6.1 RTC Control Register 15.6.2 RTC Mode Register 15.6.3 RTC Time Register 15.6.4 RTC Calendar Register 15.6.5 RTC Time Alarm Register 15.6.6 RTC Calendar Alarm Register 15.6.7 RTC Status Register 15.6.8 RTC Status Clear Command Register 15.6.9 RTC Interrupt Enable Register 15.6.10 RTC Interrupt Disable Register 15.6.11 RTC Interrupt Mask Register 15.6.12 RTC Valid Entry Register 15.6.13 RTC TimeStamp Time Register 0 (UTC_MODE) 15.6.14 RTC TimeStamp Time Register 1 (UTC_MODE) 15.6.15 RTC TimeStamp Date Register (UTC_MODE) 16. Watchdog Timer (WDT) 16.1 Description 16.2 Embedded Characteristics 16.3 Block Diagram 16.4 Functional Description 16.5 Watchdog Timer (WDT) User Interface 16.5.1 Watchdog Timer Control Register 16.5.2 Watchdog Timer Mode Register 16.5.3 Watchdog Timer Status Register 17. Reinforced Safety Watchdog Timer (RSWDT) 17.1 Description 17.2 Embedded Characteristics 17.3 Block Diagram 17.4 Functional Description 17.5 Reinforced Safety Watchdog Timer (RSWDT) User Interface 17.5.1 Reinforced Safety Watchdog Timer Control Register 17.5.2 Reinforced Safety Watchdog Timer Mode Register 17.5.3 Reinforced Safety Watchdog Timer Status Register 18. Supply Controller (SUPC) 18.1 Description 18.2 Embedded Characteristics 18.3 Block Diagram 18.4 Functional Description 18.4.1 Overview 18.4.2 Slow Clock Generator 18.4.3 Core Voltage Regulator Control/Backup Low-power Mode 18.4.4 Supply Monitor 18.4.5 Backup Power Supply Reset 18.4.5.1 Raising the Backup Power Supply 18.4.6 Core Reset 18.4.6.1 Supply Monitor Reset 18.4.6.2 Brownout Detector Reset 18.4.7 Wake-up Sources 18.4.7.1 Force Wake-up 18.4.7.2 Wake-up Inputs 18.4.7.3 Low-power Tamper Detection and Anti-Tampering 18.4.7.4 Clock Alarms 18.4.7.5 Supply Monitor Detection 18.4.8 Register Write Protection 18.4.9 Register Bits in Backup Domain (VDDIO) 18.5 Supply Controller (SUPC) User Interface 18.5.1 System Controller (SYSC) User Interface 18.5.2 Supply Controller (SUPC) User Interface 18.5.3 Supply Controller Control Register 18.5.4 Supply Controller Supply Monitor Mode Register 18.5.5 Supply Controller Mode Register 18.5.6 Supply Controller Wake-up Mode Register 18.5.7 Supply Controller Wake-up Inputs Register 18.5.8 Supply Controller Status Register 18.5.9 System Controller Write Protection Mode Register 19. General Purpose Backup Registers (GPBR) 19.1 Description 19.2 Embedded Characteristics 19.3 General Purpose Backup Registers (GPBR) User Interface 19.3.1 General Purpose Backup Register x 20. Enhanced Embedded Flash Controller (EEFC) 20.1 Description 20.2 Embedded Characteristics 20.3 Product Dependencies 20.3.1 Power Management 20.3.2 Interrupt Sources 20.4 Functional Description 20.4.1 Embedded Flash Organization 20.4.2 Read Operations 20.4.2.1 128- or 64-bit Access Mode 20.4.2.2 Code Read Optimization 20.4.2.3 Code Loop Optimization 20.4.2.4 Data Read Optimization 20.4.3 Flash Commands 20.4.3.1 Get Flash Descriptor Command 20.4.3.2 Write Commands Full Page Programming Partial Page Programming Programming Bytes 20.4.3.3 Erase Commands 20.4.3.4 Lock Bit Protection 20.4.3.5 GPNVM Bit 20.4.3.6 Calibration Bit 20.4.3.7 Security Bit Protection 20.4.3.8 Unique Identifier Area 20.4.3.9 User Signature Area 20.5 Enhanced Embedded Flash Controller (EEFC) User Interface 20.5.1 EEFC Flash Mode Register 20.5.2 EEFC Flash Command Register 20.5.3 EEFC Flash Status Register 20.5.4 EEFC Flash Result Register 21. Fast Flash Programming Interface (FFPI) 21.1 Description 21.2 Embedded Characteristics 21.3 Parallel Fast Flash Programming 21.3.1 Device Configuration 21.3.2 Signal Names 21.3.3 Entering Parallel Programming Mode 21.3.4 Programmer Handshaking 21.3.4.1 Write Handshaking 21.3.4.2 Read Handshaking 21.3.5 Device Operations 21.3.5.1 Flash Read Command 21.3.5.2 Flash Write Command 21.3.5.3 Flash Full Erase Command 21.3.5.4 Flash Lock Commands 21.3.5.5 Flash General-purpose NVM Commands 21.3.5.6 Flash Security Bit Command 21.3.5.7 Memory Write Command 21.3.5.8 Get Version Command 22. Cortex-M Cache Controller (CMCC) 22.1 Description 22.2 Embedded Characteristics 22.3 Block Diagram 22.4 Functional Description 22.4.1 Cache Operation 22.4.2 Cache Maintenance 22.4.2.1 Cache Invalidate-by-Line Operation 22.4.2.2 Cache Invalidate All Operation 22.4.3 Cache Performance Monitoring 22.5 Cortex-M Cache Controller (CMCC) User Interface 22.5.1 Cache Controller Type Register 22.5.2 Cache Controller Configuration Register 22.5.3 Cache Controller Control Register 22.5.4 Cache Controller Status Register 22.5.5 Cache Controller Maintenance Register 0 22.5.6 Cache Controller Maintenance Register 1 22.5.7 Cache Controller Monitor Configuration Register 22.5.8 Cache Controller Monitor Enable Register 22.5.9 Cache Controller Monitor Control Register 22.5.10 Cache Controller Monitor Status Register 23. SAM-BA Boot Program for SAM4E Microcontrollers 23.1 Description 23.2 Embedded Characteristics 23.3 Hardware and Software Constraints 23.4 Flow Diagram 23.5 Device Initialization 23.6 SAM-BA Monitor 23.6.1 UART0 Serial Port 23.6.2 Xmodem Protocol 23.6.3 USB Device Port 23.6.3.1 Enumeration Process 23.6.3.2 Communication Endpoints 23.6.4 In Application Programming (IAP) Feature 24. Bus Matrix (MATRIX) 24.1 Description 24.2 Embedded Characteristics 24.2.1 Matrix Masters 24.2.2 Matrix Slaves 24.2.3 Master to Slave Access 24.3 Memory Mapping 24.4 Special Bus Granting Mechanism 24.5 No Default Master 24.6 Last Access Master 24.7 Fixed Default Master 24.8 Arbitration 24.8.1 Arbitration Scheduling 24.8.1.1 Undefined Length Burst Arbitration 24.8.1.2 Slot Cycle Limit Arbitration 24.8.2 Arbitration Priority Scheme 24.8.2.1 Fixed Priority Arbitration 24.8.2.2 Round-Robin Arbitration 24.9 System I/O Configuration 24.10 SMC NAND Flash Chip Select Configuration 24.11 Write Protect Registers 24.12 Bus Matrix (MATRIX) User Interface 24.12.1 Bus Matrix Master Configuration Registers 24.12.2 Bus Matrix Slave Configuration Registers 24.12.3 Bus Matrix Priority Registers A For Slaves 24.12.4 Bus Matrix Master Remap Control Register 24.12.5 System I/O Configuration Register 24.12.6 SMC NAND Flash Chip Select Configuration Register 24.12.7 Write Protect Mode Register 24.12.8 Write Protect Status Register 25. DMA Controller (DMAC) 25.1 Description 25.2 Embedded Characteristics 25.3 DMA Controller Peripheral Connections 25.4 Block Diagram 25.5 Product Dependencies 25.5.1 Interrupt Sources 25.6 Functional Description 25.6.1 Basic Definitions 25.6.2 Memory Peripherals 25.6.3 Handshaking Interface 25.6.3.1 Software Handshaking 25.6.4 DMAC Transfer Types 25.6.4.1 Multi-buffer Transfers 25.6.4.2 Programming DMAC for Multiple Buffer Transfers 25.6.4.3 Ending Multi-buffer Transfers 25.6.5 Programming a Channel 25.6.5.1 Programming Examples 25.6.6 Disabling a Channel Prior to Transfer Completion 25.6.6.1 Abnormal Transfer Termination 25.6.7 Register Write Protection 25.7 DMAC Software Requirements 25.8 DMA Controller (DMAC) User Interface 25.8.1 DMAC Global Configuration Register 25.8.2 DMAC Enable Register 25.8.3 DMAC Software Single Request Register 25.8.4 DMAC Software Chunk Transfer Request Register 25.8.5 DMAC Software Last Transfer Flag Register 25.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register 25.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register 25.8.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register 25.8.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register 25.8.10 DMAC Channel Handler Enable Register 25.8.11 DMAC Channel Handler Disable Register 25.8.12 DMAC Channel Handler Status Register 25.8.13 DMAC Channel x [x = 0..3] Source Address Register 25.8.14 DMAC Channel x [x = 0..3] Destination Address Register 25.8.15 DMAC Channel x [x = 0..3] Descriptor Address Register 25.8.16 DMAC Channel x [x = 0..3] Control A Register 25.8.17 DMAC Channel x [x = 0..3] Control B Register 25.8.18 DMAC Channel x [x = 0..3] Configuration Register 25.8.19 DMAC Write Protection Mode Register 25.8.20 DMAC Write Protection Status Register 26. Peripheral DMA Controller (PDC) 26.1 Description 26.2 Embedded Characteristics 26.3 Block Diagram 26.4 Functional Description 26.4.1 Configuration 26.4.2 Memory Pointers 26.4.3 Transfer Counters 26.4.4 Data Transfers 26.4.5 PDC Flags and Peripheral Status Register 26.4.5.1 Receive Transfer End 26.4.5.2 Transmit Transfer End 26.4.5.3 Receive Buffer Full 26.4.5.4 Transmit Buffer Empty 26.5 Peripheral DMA Controller (PDC) User Interface 26.5.1 Receive Pointer Register 26.5.2 Receive Counter Register 26.5.3 Transmit Pointer Register 26.5.4 Transmit Counter Register 26.5.5 Receive Next Pointer Register 26.5.6 Receive Next Counter Register 26.5.7 Transmit Next Pointer Register 26.5.8 Transmit Next Counter Register 26.5.9 Transfer Control Register 26.5.10 Transfer Status Register 27. Static Memory Controller (SMC) 27.1 Description 27.2 Embedded Characteristics 27.3 I/O Lines Description 27.4 Multiplexed Signals 27.5 Product Dependencies 27.5.1 I/O Lines 27.5.2 Power Management 27.6 External Memory Mapping 27.7 Connection to External Devices 27.7.1 Data Bus Width 27.7.2 NAND Flash Support 27.8 Application Example 27.8.1 Implementation Examples 27.8.1.1 8-bit NAND Flash Hardware Configuration Software Configuration 27.8.1.2 NOR Flash Hardware Configuration Software Configuration 27.9 Standard Read and Write Protocols 27.9.1 Read Waveforms 27.9.1.1 NRD Waveform 27.9.1.2 NCS Waveform 27.9.1.3 Read Cycle 27.9.1.4 Null Delay Setup and Hold 27.9.1.5 Null Pulse 27.9.2 Read Mode 27.9.2.1 Read is Controlled by NRD (SMC_MODE.READ_MODE = 1): 27.9.2.2 Read is Controlled by NCS (SMC_MODE.READ_MODE = 0) 27.9.3 Write Waveforms 27.9.3.1 NWE Waveforms 27.9.3.2 NCS Waveforms 27.9.3.3 Write Cycle 27.9.3.4 Null Delay Setup and Hold 27.9.3.5 Null Pulse 27.9.4 Write Mode 27.9.4.1 Write is Controlled by NWE (SMC.MODE.WRITE_MODE = 1): 27.9.4.2 Write is Controlled by NCS (SMC.MODE.WRITE_MODE = 0) 27.9.5 Register Write Protection 27.9.6 Coding Timing Parameters 27.9.7 Reset Values of Timing Parameters 27.9.8 Usage Restriction 27.10 Scrambling/Unscrambling Function 27.11 Automatic Wait States 27.11.1 Chip Select Wait States 27.11.2 Early Read Wait State 27.11.3 Reload User Configuration Wait State 27.11.3.1 User Procedure 27.11.3.2 Slow Clock Mode Transition 27.11.4 Read to Write Wait State 27.12 Data Float Wait States 27.12.1 SMC_MODE.READ_MODE 27.12.2 TDF Optimization Enabled (SMC_MODE.TDF_MODE = 1) 27.12.3 TDF Optimization Disabled (SMC_MODE.TDF_MODE = 0) 27.13 External Wait 27.13.1 Restriction 27.13.2 Frozen Mode 27.13.3 Ready Mode 27.13.4 NWAIT Latency and Read/Write Timings 27.14 Slow Clock Mode 27.14.1 Slow Clock Mode Waveforms 27.14.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 27.15 Asynchronous Page Mode 27.15.1 Protocol and Timings in Page Mode 27.15.2 Page Mode Restriction 27.15.3 Sequential and Non-sequential Accesses 27.16 Static Memory Controller (SMC) User Interface 27.16.1 SMC Setup Register 27.16.2 SMC Pulse Register 27.16.3 SMC Cycle Register 27.16.4 SMC Mode Register 27.16.5 SMC Off-Chip Memory Scrambling Register 27.16.6 SMC Off-Chip Memory Scrambling Key1 Register 27.16.7 SMC Off-Chip Memory Scrambling Key2 Register 27.16.8 SMC Write Protection Mode Register 27.16.9 SMC Write Protection Status Register 28. Clock Generator 28.1 Description 28.2 Embedded Characteristics 28.3 Block Diagram 28.4 Slow Clock 28.4.1 Embedded 32 kHz (typical) RC Oscillator 28.4.2 32768 Hz Crystal Oscillator 28.5 Main Clock 28.5.1 Embedded 4/8/12 MHz RC Oscillator 28.5.2 4/8/12 MHz RC Oscillator Clock Frequency Adjustment 28.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator 28.5.4 Main Clock Source Selection 28.5.5 Bypassing the 3 to 20 MHz Crystal Oscillator 28.5.6 Main Clock Frequency Counter 28.5.7 Switching Main Clock between the RC Oscillator and the Crystal Oscillator 28.6 Divider and PLL Block 28.6.1 Divider and Phase Lock Loop Programming 29. Power Management Controller (PMC) 29.1 Description 29.2 Embedded Characteristics 29.3 Block Diagram 29.4 Master Clock Controller 29.5 Processor Clock Controller 29.6 SysTick Clock 29.7 USB Clock Controller 29.8 Peripheral Clock Controller 29.9 Free-Running Processor Clock 29.10 Programmable Clock Output Controller 29.11 Fast Startup 29.12 Startup from Embedded Flash 29.13 Main Clock Failure Detector 29.14 32768 Hz Crystal Oscillator Frequency Monitor 29.15 Programming Sequence 29.16 Clock Switching Details 29.16.1 Master Clock Switching Timings 29.16.2 Clock Switching Waveforms 29.17 Register Write Protection 29.18 Power Management Controller (PMC) User Interface 29.18.1 PMC System Clock Enable Register 29.18.2 PMC System Clock Disable Register 29.18.3 PMC System Clock Status Register 29.18.4 PMC Peripheral Clock Enable Register 0 29.18.5 PMC Peripheral Clock Disable Register 0 29.18.6 PMC Peripheral Clock Status Register 0 29.18.7 PMC Clock Generator Main Oscillator Register 29.18.8 PMC Clock Generator Main Clock Frequency Register 29.18.9 PMC Clock Generator PLLA Register 29.18.10 PMC Master Clock Register 29.18.11 PMC USB Clock Register 29.18.12 PMC Programmable Clock Register 29.18.13 PMC Interrupt Enable Register 29.18.14 PMC Interrupt Disable Register 29.18.15 PMC Status Register 29.18.16 PMC Interrupt Mask Register 29.18.17 PMC Fast Startup Mode Register 29.18.18 PMC Fast Startup Polarity Register 29.18.19 PMC Fault Output Clear Register 29.18.20 PMC Write Protection Mode Register 29.18.21 PMC Write Protection Status Register 29.18.22 PMC Peripheral Clock Enable Register 1 29.18.23 PMC Peripheral Clock Disable Register 1 29.18.24 PMC Peripheral Clock Status Register 1 29.18.25 PMC Oscillator Calibration Register 29.18.26 PLL Maximum Multiplier Value Register 30. Advanced Encryption Standard (AES) 30.1 Description 30.2 Embedded Characteristics 30.3 Product Dependencies 30.3.1 Power Management 30.3.2 Interrupt Sources 30.4 Functional Description 30.4.1 AES Register Endianness 30.4.2 Operation Modes 30.4.3 Double Input Buffer 30.4.4 Start Modes 30.4.4.1 Manual Mode 30.4.4.2 Auto Mode 30.4.4.3 DMA Mode 30.4.5 Last Output Data Mode 30.4.5.1 Manual and Auto Modes If AES_MR.LOD = 0 If AES_MR.LOD = 1 30.4.5.2 DMA Mode If AES_MR.LOD = 0 If AES_MR.LOD = 1 30.4.6 Security Features 30.4.6.1 Unspecified Register Access Detection 30.5 Advanced Encryption Standard (AES) User Interface 30.5.1 AES Control Register 30.5.2 AES Mode Register 30.5.3 AES Interrupt Enable Register 30.5.4 AES Interrupt Disable Register 30.5.5 AES Interrupt Mask Register 30.5.6 AES Interrupt Status Register 30.5.7 AES Key Word Register x 30.5.8 AES Input Data Register x 30.5.9 AES Output Data Register x 30.5.10 AES Initialization Vector Register x 31. Controller Area Network (CAN) 31.1 Description 31.2 Embedded Characteristics 31.3 Block Diagram 31.4 Application Block Diagram 31.5 I/O Lines Description 31.6 Product Dependencies 31.6.1 I/O Lines 31.6.2 Power Management 31.6.3 Interrupt Sources 31.7 CAN Controller Features 31.7.1 CAN Protocol Overview 31.7.2 Mailbox Organization 31.7.2.1 Message Acceptance Procedure 31.7.2.2 Receive Mailbox 31.7.2.3 Transmit Mailbox 31.7.3 Time Management Unit 31.7.4 CAN 2.0 Standard Features 31.7.4.1 CAN Bit Timing Configuration 31.7.4.2 Error Detection 31.7.4.3 Overload 31.7.5 Low-power Mode 31.7.5.1 Enabling Low-power Mode 31.7.5.2 Disabling Low-power Mode 31.8 Functional Description 31.8.1 CAN Controller Initialization 31.8.2 CAN Controller Interrupt Handling 31.8.3 CAN Controller Message Handling 31.8.3.1 Receive Handling 31.8.3.2 Transmission Handling 31.8.3.3 Remote Frame Handling 31.8.4 CAN Controller Timing Modes 31.8.4.1 Timestamping Mode 31.8.4.2 Time Triggered Mode 31.8.5 Register Write Protection 31.9 Controller Area Network (CAN) User Interface 31.9.1 CAN Mode Register 31.9.2 CAN Interrupt Enable Register 31.9.3 CAN Interrupt Disable Register 31.9.4 CAN Interrupt Mask Register 31.9.5 CAN Status Register 31.9.6 CAN Baudrate Register 31.9.7 CAN Timer Register 31.9.8 CAN Timestamp Register 31.9.9 CAN Error Counter Register 31.9.10 CAN Transfer Command Register 31.9.11 CAN Abort Command Register 31.9.12 CAN Write Protection Mode Register 31.9.13 CAN Write Protection Status Register 31.9.14 CAN Message Mode Register 31.9.15 CAN Message Acceptance Mask Register 31.9.16 CAN Message ID Register 31.9.17 CAN Message Family ID Register 31.9.18 CAN Message Status Register 31.9.19 CAN Message Data Low Register 31.9.20 CAN Message Data High Register 31.9.21 CAN Message Control Register 32. Chip Identifier (CHIPID) 32.1 Description 32.2 Embedded Characteristics 32.3 Chip Identifier (CHIPID) User Interface 32.3.1 Chip ID Register 32.3.2 Chip ID Extension Register 33. Parallel Input/Output Controller (PIO) 33.1 Description 33.2 Embedded Characteristics 33.3 Block Diagram 33.4 Product Dependencies 33.4.1 Pin Multiplexing 33.4.2 Power Management 33.4.3 Interrupt Sources 33.5 Functional Description 33.5.1 Pull-up and Pull-down Resistor Control 33.5.2 I/O Line or Peripheral Function Selection 33.5.3 Peripheral A or B or C or D Selection 33.5.4 Output Control 33.5.5 Synchronous Data Output 33.5.6 Multi-Drive Control (Open Drain) 33.5.7 Output Line Timings 33.5.8 Inputs 33.5.9 Input Glitch and Debouncing Filters 33.5.10 Input Edge/Level Interrupt 33.5.11 I/O Lines Lock 33.5.12 Programmable I/O Delays 33.5.13 Programmable Schmitt Trigger 33.5.14 Parallel Capture Mode 33.5.14.1 Overview 33.5.14.2 Functional Description 33.5.14.3 Restrictions 33.5.14.4 Programming Sequence 33.5.15 I/O Lines Programming Example 33.5.16 Register Write Protection 33.6 Parallel Input/Output Controller (PIO) User Interface 33.6.1 PIO Enable Register 33.6.2 PIO Disable Register 33.6.3 PIO Status Register 33.6.4 PIO Output Enable Register 33.6.5 PIO Output Disable Register 33.6.6 PIO Output Status Register 33.6.7 PIO Input Filter Enable Register 33.6.8 PIO Input Filter Disable Register 33.6.9 PIO Input Filter Status Register 33.6.10 PIO Set Output Data Register 33.6.11 PIO Clear Output Data Register 33.6.12 PIO Output Data Status Register 33.6.13 PIO Pin Data Status Register 33.6.14 PIO Interrupt Enable Register 33.6.15 PIO Interrupt Disable Register 33.6.16 PIO Interrupt Mask Register 33.6.17 PIO Interrupt Status Register 33.6.18 PIO Multi-driver Enable Register 33.6.19 PIO Multi-driver Disable Register 33.6.20 PIO Multi-driver Status Register 33.6.21 PIO Pull-Up Disable Register 33.6.22 PIO Pull-Up Enable Register 33.6.23 PIO Pull-Up Status Register 33.6.24 PIO Peripheral ABCD Select Register 1 33.6.25 PIO Peripheral ABCD Select Register 2 33.6.26 PIO Input Filter Slow Clock Disable Register 33.6.27 PIO Input Filter Slow Clock Enable Register 33.6.28 PIO Input Filter Slow Clock Status Register 33.6.29 PIO Slow Clock Divider Debouncing Register 33.6.30 PIO Pad Pull-Down Disable Register 33.6.31 PIO Pad Pull-Down Enable Register 33.6.32 PIO Pad Pull-Down Status Register 33.6.33 PIO Output Write Enable Register 33.6.34 PIO Output Write Disable Register 33.6.35 PIO Output Write Status Register 33.6.36 PIO Additional Interrupt Modes Enable Register 33.6.37 PIO Additional Interrupt Modes Disable Register 33.6.38 PIO Additional Interrupt Modes Mask Register 33.6.39 PIO Edge Select Register 33.6.40 PIO Level Select Register 33.6.41 PIO Edge/Level Status Register 33.6.42 PIO Falling Edge/Low-Level Select Register 33.6.43 PIO Rising Edge/High-Level Select Register 33.6.44 PIO Fall/Rise - Low/High Status Register 33.6.45 PIO Lock Status Register 33.6.46 PIO Write Protection Mode Register 33.6.47 PIO Write Protection Status Register 33.6.48 PIO Schmitt Trigger Register 33.6.49 PIO I/O Delay Register 33.6.50 PIO Parallel Capture Mode Register 33.6.51 PIO Parallel Capture Interrupt Enable Register 33.6.52 PIO Parallel Capture Interrupt Disable Register 33.6.53 PIO Parallel Capture Interrupt Mask Register 33.6.54 PIO Parallel Capture Interrupt Status Register 33.6.55 PIO Parallel Capture Reception Holding Register 34. Serial Peripheral Interface (SPI) 34.1 Description 34.2 Embedded Characteristics 34.3 Block Diagram 34.4 Application Block Diagram 34.5 Signal Description 34.6 Product Dependencies 34.6.1 I/O Lines 34.6.2 Power Management 34.6.3 Interrupt 34.6.4 Peripheral DMA Controller (PDC) or Direct Memory Access Controller (DMAC) 34.7 Functional Description 34.7.1 Modes of Operation 34.7.2 Data Transfer 34.7.3 Master Mode Operations 34.7.3.1 Master Mode Block Diagram 34.7.3.2 Master Mode Flow Diagram 34.7.3.3 Clock Generation 34.7.3.4 Transfer Delays 34.7.3.5 Peripheral Selection 34.7.3.6 SPI Peripheral DMA Controller (PDC) Transfer Size 34.7.3.7 SPI Direct Access Memory Controller (DMAC) 34.7.3.8 Peripheral Chip Select Decoding 34.7.3.9 Peripheral Deselection without DMA nor PDC 34.7.3.10 Peripheral Deselection with DMA or PDC 34.7.3.11 Mode Fault Detection 34.7.4 SPI Slave Mode 34.7.5 Register Write Protection 34.8 Serial Peripheral Interface (SPI) User Interface 34.8.1 SPI Control Register 34.8.2 SPI Mode Register 34.8.3 SPI Receive Data Register 34.8.4 SPI Transmit Data Register 34.8.5 SPI Status Register 34.8.6 SPI Interrupt Enable Register 34.8.7 SPI Interrupt Disable Register 34.8.8 SPI Interrupt Mask Register 34.8.9 SPI Chip Select Register 34.8.10 SPI Write Protection Mode Register 34.8.11 SPI Write Protection Status Register 35. Two-wire Interface (TWI) 35.1 Description 35.2 Embedded Characteristics 35.3 List of Abbreviations 35.4 Block Diagram 35.5 I/O Lines Description 35.6 Product Dependencies 35.6.1 I/O Lines 35.6.2 Power Management 35.6.3 Interrupt Sources 35.7 Functional Description 35.7.1 Transfer Format 35.7.2 Modes of Operation 35.7.3 Master Mode 35.7.3.1 Definition 35.7.3.2 Programming Master Mode 35.7.3.3 Master Transmitter Mode 35.7.3.4 Master Receiver Mode 35.7.3.5 Internal Address 35.7.3.6 Using the Peripheral DMA Controller (PDC) 35.7.3.7 SMBus Quick Command (Master Mode Only) 35.7.3.8 Read/Write Flowcharts 35.7.4 Multi-master Mode 35.7.4.1 Definition 35.7.4.2 Two Multi-master Modes 35.7.5 Slave Mode 35.7.5.1 Definition 35.7.5.2 Programming Slave Mode 35.7.5.3 Receiving Data 35.7.5.4 Data Transfer Clock Stretching in Read Mode Clock Synchronization in Write Mode Reversal of Read to Write Reversal of Write to Read 35.7.5.5 Using the Peripheral DMA Controller (PDC) in Slave Mode 35.7.5.6 Read Write Flowcharts 35.7.6 Register Write Protection 35.8 Two-wire Interface (TWI) User Interface 35.8.1 TWI Control Register 35.8.2 TWI Master Mode Register 35.8.3 TWI Slave Mode Register 35.8.4 TWI Internal Address Register 35.8.5 TWI Clock Waveform Generator Register 35.8.6 TWI Status Register 35.8.7 TWI Interrupt Enable Register 35.8.8 TWI Interrupt Disable Register 35.8.9 TWI Interrupt Mask Register 35.8.10 TWI Receive Holding Register 35.8.11 TWI Transmit Holding Register 35.8.12 TWI Write Protection Mode Register 35.8.13 TWI Write Protection Status Register 36. Universal Asynchronous Receiver Transmitter (UART) 36.1 Description 36.2 Embedded Characteristics 36.3 Block Diagram 36.4 Product Dependencies 36.4.1 I/O Lines 36.4.2 Power Management 36.4.3 Interrupt Sources 36.5 Functional Description 36.5.1 Baud Rate Generator 36.5.2 Receiver 36.5.2.1 Receiver Reset, Enable and Disable 36.5.2.2 Start Detection and Data Sampling 36.5.2.3 Receiver Ready 36.5.2.4 Receiver Overrun 36.5.2.5 Parity Error 36.5.2.6 Receiver Framing Error 36.5.3 Transmitter 36.5.3.1 Transmitter Reset, Enable and Disable 36.5.3.2 Transmit Format 36.5.3.3 Transmitter Control 36.5.4 Peripheral DMA Controller (PDC) 36.5.5 Test Modes 36.6 Universal Asynchronous Receiver Transmitter (UART) User Interface 36.6.1 UART Control Register 36.6.2 UART Mode Register 36.6.3 UART Interrupt Enable Register 36.6.4 UART Interrupt Disable Register 36.6.5 UART Interrupt Mask Register 36.6.6 UART Status Register 36.6.7 UART Receiver Holding Register 36.6.8 UART Transmit Holding Register 36.6.9 UART Baud Rate Generator Register 37. Universal Synchronous Asynchronous Receiver Transmitter (USART) 37.1 Description 37.2 Embedded Characteristics 37.3 Block Diagram 37.4 I/O Lines Description 37.5 Product Dependencies 37.5.1 I/O Lines 37.5.2 Power Management 37.5.3 Interrupt Sources 37.6 Functional Description 37.6.1 Baud Rate Generator 37.6.1.1 Baud Rate in Asynchronous Mode Baud Rate Calculation Example 37.6.1.2 Fractional Baud Rate in Asynchronous Mode 37.6.1.3 Baud Rate in Synchronous Mode or SPI Mode 37.6.1.4 Baud Rate in ISO 7816 Mode 37.6.2 Receiver and Transmitter Control 37.6.3 Synchronous and Asynchronous Modes 37.6.3.1 Transmitter Operations 37.6.3.2 Manchester Encoder Drift Compensation 37.6.3.3 Asynchronous Receiver 37.6.3.4 Manchester Decoder 37.6.3.5 Radio Interface: Manchester Encoded USART Application 37.6.3.6 Synchronous Receiver 37.6.3.7 Receiver Operations 37.6.3.8 Parity 37.6.3.9 Multidrop Mode 37.6.3.10 Transmitter Timeguard 37.6.3.11 Receiver Time-out 37.6.3.12 Framing Error 37.6.3.13 Transmit Break 37.6.3.14 Receive Break 37.6.3.15 Hardware Handshaking 37.6.4 ISO7816 Mode 37.6.4.1 ISO7816 Mode Overview 37.6.4.2 Protocol T = 0 Receive Error Counter Receive NACK Inhibit Transmit Character Repetition Disable Successive Receive NACK 37.6.4.3 Protocol T = 1 37.6.5 IrDA Mode 37.6.5.1 IrDA Modulation 37.6.5.2 IrDA Baud Rate 37.6.5.3 IrDA Demodulator 37.6.6 RS485 Mode 37.6.7 Modem Mode 37.6.8 SPI Mode 37.6.8.1 Modes of Operation 37.6.8.2 Baud Rate 37.6.8.3 Data Transfer 37.6.8.4 Receiver and Transmitter Control 37.6.8.5 Character Transmission 37.6.8.6 Character Reception 37.6.8.7 Receiver Timeout 37.6.9 Test Modes 37.6.9.1 Normal Mode 37.6.9.2 Automatic Echo Mode 37.6.9.3 Local Loopback Mode 37.6.9.4 Remote Loopback Mode 37.6.10 Register Write Protection 37.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface 37.7.1 USART Control Register 37.7.2 USART Control Register (SPI_MODE) 37.7.3 USART Mode Register 37.7.4 USART Mode Register (SPI_MODE) 37.7.5 USART Interrupt Enable Register 37.7.6 USART Interrupt Enable Register (SPI_MODE) 37.7.7 USART Interrupt Disable Register 37.7.8 USART Interrupt Disable Register (SPI_MODE) 37.7.9 USART Interrupt Mask Register 37.7.10 USART Interrupt Mask Register (SPI_MODE) 37.7.11 USART Channel Status Register 37.7.12 USART Channel Status Register (SPI_MODE) 37.7.13 USART Receive Holding Register 37.7.14 USART Transmit Holding Register 37.7.15 USART Baud Rate Generator Register 37.7.16 USART Receiver Time-out Register 37.7.17 USART Transmitter Timeguard Register 37.7.18 USART FI DI RATIO Register 37.7.19 USART Number of Errors Register 37.7.20 USART IrDA Filter Register 37.7.21 USART Manchester Configuration Register 37.7.22 USART Write Protection Mode Register 37.7.23 USART Write Protection Status Register 38. Timer Counter (TC) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 Pin List 38.5 Product Dependencies 38.5.1 I/O Lines 38.5.2 Power Management 38.5.3 Interrupt Sources 38.5.4 Synchronization Inputs from PWM 38.5.5 Fault Output 38.6 Functional Description 38.6.1 Description 38.6.2 32-bit Counter 38.6.3 Clock Selection 38.6.4 Clock Control 38.6.5 Operating Modes 38.6.6 Trigger 38.6.7 Capture Mode 38.6.8 Capture Registers A and B 38.6.9 Transfer with PDC in Capture Mode 38.6.10 Trigger Conditions 38.6.11 Waveform Mode 38.6.12 Waveform Selection 38.6.12.1 WAVSEL = 00 38.6.12.2 WAVSEL = 10 38.6.12.3 WAVSEL = 01 38.6.12.4 WAVSEL = 11 38.6.13 External Event/Trigger Conditions 38.6.14 Synchronization with PWM 38.6.15 Output Controller 38.6.16 Quadrature Decoder 38.6.16.1 Description 38.6.16.2 Input Pre-processing 38.6.16.3 Direction Status and Change Detection 38.6.16.4 Position and Rotation Measurement 38.6.16.5 Speed Measurement 38.6.16.6 Detecting a Missing Index Pulse 38.6.17 2-bit Gray Up/Down Counter for Stepper Motor 38.6.18 Fault Mode 38.6.19 Register Write Protection 38.7 Timer Counter (TC) User Interface 38.7.1 TC Channel Control Register 38.7.2 TC Channel Mode Register: Capture Mode 38.7.3 TC Channel Mode Register: Waveform Mode 38.7.4 TC Stepper Motor Mode Register 38.7.5 TC Register AB 38.7.6 TC Counter Value Register 38.7.7 TC Register A 38.7.8 TC Register B 38.7.9 TC Register C 38.7.10 TC Status Register 38.7.11 TC Interrupt Enable Register 38.7.12 TC Interrupt Disable Register 38.7.13 TC Interrupt Mask Register 38.7.14 TC Extended Mode Register 38.7.15 TC Block Control Register 38.7.16 TC Block Mode Register 38.7.17 TC QDEC Interrupt Enable Register 38.7.18 TC QDEC Interrupt Disable Register 38.7.19 TC QDEC Interrupt Mask Register 38.7.20 TC QDEC Interrupt Status Register 38.7.21 TC Fault Mode Register 38.7.22 TC Write Protection Mode Register 39. Pulse Width Modulation Controller (PWM) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.4 I/O Lines Description 39.5 Product Dependencies 39.5.1 I/O Lines 39.5.2 Power Management 39.5.3 Interrupt Sources 39.5.4 Fault Inputs 39.6 Functional Description 39.6.1 PWM Clock Generator 39.6.2 PWM Channel 39.6.2.1 Channel Block Diagram 39.6.2.2 Comparator 39.6.2.3 Trigger Selection for Timer Counter Delay Measurement Cumulated ON Time Measurement 39.6.2.4 2-bit Gray Up/Down Counter for Stepper Motor 39.6.2.5 Dead-Time Generator 39.6.2.6 Output Override 39.6.2.7 Fault Protection 39.6.2.8 Spread Spectrum Counter 39.6.2.9 Synchronous Channels Method 1: Manual write of duty-cycle values and manual trigger of the update Method 2: Manual write of duty-cycle values and automatic trigger of the update Method 3: Automatic write of duty-cycle values and automatic trigger of the update 39.6.2.10 Update Time for Double-Buffering Registers 39.6.3 PWM Comparison Units 39.6.4 PWM Event Lines 39.6.5 PWM Controller Operations 39.6.5.1 Initialization 39.6.5.2 Source Clock Selection Criteria 39.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times 39.6.5.4 Changing the Update Period of Synchronous Channels 39.6.5.5 Changing the Comparison Value and the Comparison Configuration 39.6.5.6 Interrupt Sources 39.6.6 Register Write Protection 39.7 Pulse Width Modulation Controller (PWM) User Interface 39.7.1 PWM Clock Register 39.7.2 PWM Enable Register 39.7.3 PWM Disable Register 39.7.4 PWM Status Register 39.7.5 PWM Interrupt Enable Register 1 39.7.6 PWM Interrupt Disable Register 1 39.7.7 PWM Interrupt Mask Register 1 39.7.8 PWM Interrupt Status Register 1 39.7.9 PWM Sync Channels Mode Register 39.7.10 PWM DMA Register 39.7.11 PWM Sync Channels Update Control Register 39.7.12 PWM Sync Channels Update Period Register 39.7.13 PWM Sync Channels Update Period Update Register 39.7.14 PWM Interrupt Enable Register 2 39.7.15 PWM Interrupt Disable Register 2 39.7.16 PWM Interrupt Mask Register 2 39.7.17 PWM Interrupt Status Register 2 39.7.18 PWM Output Override Value Register 39.7.19 PWM Output Selection Register 39.7.20 PWM Output Selection Set Register 39.7.21 PWM Output Selection Clear Register 39.7.22 PWM Output Selection Set Update Register 39.7.23 PWM Output Selection Clear Update Register 39.7.24 PWM Fault Mode Register 39.7.25 PWM Fault Status Register 39.7.26 PWM Fault Clear Register 39.7.27 PWM Fault Protection Value Register 1 39.7.28 PWM Fault Protection Enable Register 39.7.29 PWM Event Line x Register 39.7.30 PWM Spread Spectrum Register 39.7.31 PWM Spread Spectrum Update Register 39.7.32 PWM Stepper Motor Mode Register 39.7.33 PWM Fault Protection Value Register 2 39.7.34 PWM Write Protection Control Register 39.7.35 PWM Write Protection Status Register 39.7.36 PWM Comparison x Value Register 39.7.37 PWM Comparison x Value Update Register 39.7.38 PWM Comparison x Mode Register 39.7.39 PWM Comparison x Mode Update Register 39.7.40 PWM Channel Mode Register 39.7.41 PWM Channel Duty Cycle Register 39.7.42 PWM Channel Duty Cycle Update Register 39.7.43 PWM Channel Period Register 39.7.44 PWM Channel Period Update Register 39.7.45 PWM Channel Counter Register 39.7.46 PWM Channel Dead Time Register 39.7.47 PWM Channel Dead Time Update Register 39.7.48 PWM Channel Mode Update Register 40. High Speed Multimedia Card Interface (HSMCI) 40.1 Description 40.2 Embedded Characteristics 40.3 Block Diagram 40.4 Application Block Diagram 40.5 Pin Name List 40.6 Product Dependencies 40.6.1 I/O Lines 40.6.2 Power Management 40.6.3 Interrupt Sources 40.7 Bus Topology 40.8 High Speed MultiMedia Card Operations 40.8.1 Command - Response Operation 40.8.2 Data Transfer Operation 40.8.3 Read Operation 40.8.4 Write Operation 40.9 SD/SDIO Card Operation 40.9.1 SDIO Data Transfer Type 40.9.2 SDIO Interrupts 40.10 CE-ATA Operation 40.10.1 Executing an ATA Polling Command 40.10.2 Executing an ATA Interrupt Command 40.10.3 Aborting an ATA Command 40.10.4 CE-ATA Error Recovery 40.11 HSMCI Boot Operation Mode 40.11.1 Boot Procedure, Processor Mode 40.12 HSMCI Transfer Done Timings 40.12.1 Definition 40.12.2 Read Access 40.12.3 Write Access 40.13 Register Write Protection 40.14 High Speed MultiMedia Card Interface (HSMCI) User Interface 40.14.1 HSMCI Control Register 40.14.2 HSMCI Mode Register 40.14.3 HSMCI Data Timeout Register 40.14.4 HSMCI SDCard/SDIO Register 40.14.5 HSMCI Argument Register 40.14.6 HSMCI Command Register 40.14.7 HSMCI Block Register 40.14.8 HSMCI Completion Signal Timeout Register 40.14.9 HSMCI Response Register 40.14.10 HSMCI Receive Data Register 40.14.11 HSMCI Transmit Data Register 40.14.12 HSMCI Status Register 40.14.13 HSMCI Interrupt Enable Register 40.14.14 HSMCI Interrupt Disable Register 40.14.15 HSMCI Interrupt Mask Register 40.14.16 HSMCI Configuration Register 40.14.17 HSMCI Write Protection Mode Register 40.14.18 HSMCI Write Protection Status Register 40.14.19 HSMCI FIFOx Memory Aperture 41. USB Device Port (UDP) 41.1 Description 41.2 Embedded Characteristics 41.3 Block Diagram 41.3.1 Signal Description 41.4 Product Dependencies 41.4.1 I/O Lines 41.4.2 Power Management 41.4.3 Interrupt 41.5 Typical Connection 41.5.1 USB Device Transceiver 41.5.2 VBUS Monitoring 41.6 Functional Description 41.6.1 USB 2.0 Full-speed Introduction 41.6.1.1 USB 2.0 Full-speed Transfer Types 41.6.1.2 USB Bus Transactions 41.6.1.3 USB Transfer Event Definitions 41.6.2 Handling Transactions with USB 2.0 Device Peripheral 41.6.2.1 Setup Transaction 41.6.2.2 Data IN Transaction Using Endpoints Without Ping-pong Attributes Using Endpoints With Ping-pong Attribute 41.6.2.3 Data OUT Transaction Data OUT Transaction Without Ping-pong Attributes Using Endpoints With Ping-pong Attributes 41.6.2.4 Stall Handshake 41.6.2.5 Transmit Data Cancellation Endpoints Without Dual-Banks Endpoints With Dual-Banks 41.6.3 Controlling Device States 41.6.3.1 Not Powered State 41.6.3.2 Entering Attached State 41.6.3.3 From Powered State to Default State 41.6.3.4 From Default State to Address State 41.6.3.5 From Address State to Configured State 41.6.3.6 Entering in Suspend State 41.6.3.7 Receiving a Host Resume 41.6.3.8 Sending a Device Remote Wakeup Request 41.7 USB Device Port (UDP) User Interface 41.7.1 UDP Frame Number Register 41.7.2 UDP Global State Register 41.7.3 UDP Function Address Register 41.7.4 UDP Interrupt Enable Register 41.7.5 UDP Interrupt Disable Register 41.7.6 UDP Interrupt Mask Register 41.7.7 UDP Interrupt Status Register 41.7.8 UDP Interrupt Clear Register 41.7.9 UDP Reset Endpoint Register 41.7.10 UDP Endpoint Control and Status Register (CONTROL_BULK) 41.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS) 41.7.12 UDP FIFO Data Register 41.7.13 UDP Transceiver Control Register 42. Ethernet MAC (GMAC) 42.1 Description 42.2 Embedded Characteristics 42.3 Block Diagram 42.4 Signal Interfaces 42.5 Product Dependencies 42.5.1 I/O Lines 42.5.2 Power Management 42.5.3 Interrupt Sources 42.6 Functional Description 42.6.1 Media Access Controller 42.6.2 1588 Time Stamp Unit 42.6.3 AHB Direct Memory Access Interface 42.6.3.1 Receive AHB Buffers 42.6.3.2 Transmit AHB Buffers 42.6.3.3 DMA Bursting on the AHB 42.6.4 MAC Transmit Block 42.6.5 MAC Receive Block 42.6.6 Checksum Offload for IP, TCP and UDP 42.6.6.1 Receiver Checksum Offload 42.6.7 MAC Filtering Block 42.6.8 Broadcast Address 42.6.9 Hash Addressing 42.6.10 Copy all Frames (Promiscuous Mode) 42.6.11 Disable Copy of Pause Frames 42.6.12 VLAN Support 42.6.13 IEEE 1588 Support 42.6.14 Time Stamp Unit 42.6.15 MAC 802.3 Pause Frame Support 42.6.15.1 802.3 Pause Frame Reception 42.6.15.2 802.3 Pause Frame Transmission 42.6.16 MAC PFC Priority-based Pause Frame Support 42.6.16.1 PFC Pause Frame Reception 42.6.16.2 PFC Pause Frame Transmission 42.6.17 PHY Interface 42.6.18 10/100 Operation 42.6.19 Jumbo Frames 42.7 Programming Interface 42.7.1 Initialization 42.7.1.1 Configuration 42.7.1.2 Receive Buffer List 42.7.1.3 Transmit Buffer List 42.7.1.4 Address Matching 42.7.1.5 PHY Maintenance 42.7.1.6 Interrupts 42.7.1.7 Transmitting Frames 42.7.1.8 Receiving Frames 42.8 Ethernet MAC (GMAC) User Interface 42.8.1 GMAC Network Control Register 42.8.2 GMAC Network Configuration Register 42.8.3 GMAC Network Status Register 42.8.4 GMAC User Register 42.8.5 GMAC DMA Configuration Register 42.8.6 GMAC Transmit Status Register 42.8.7 GMAC Receive Buffer Queue Base Address Register 42.8.8 GMAC Transmit Buffer Queue Base Address Register 42.8.9 GMAC Receive Status Register 42.8.10 GMAC Interrupt Status Register 42.8.11 GMAC Interrupt Enable Register 42.8.12 GMAC Interrupt Disable Register 42.8.13 GMAC Interrupt Mask Register 42.8.14 GMAC PHY Maintenance Register 42.8.15 GMAC Receive Pause Quantum Register 42.8.16 GMAC Transmit Pause Quantum Register 42.8.17 GMAC Hash Register Bottom 42.8.18 GMAC Hash Register Top 42.8.19 GMAC Specific Address 1 Bottom Register 42.8.20 GMAC Specific Address 1 Top Register 42.8.21 GMAC Specific Address 2 Bottom Register 42.8.22 GMAC Specific Address 2 Top Register 42.8.23 GMAC Specific Address 3 Bottom Register 42.8.24 GMAC Specific Address 3 Top Register 42.8.25 GMAC Specific Address 4 Bottom Register 42.8.26 GMAC Specific Address 4 Top Register 42.8.27 GMAC Type ID Match 1 Register 42.8.28 GMAC Type ID Match 2 Register 42.8.29 GMAC Type ID Match 3 Register 42.8.30 GMAC Type ID Match 4 Register 42.8.31 GMAC IPG Stretch Register 42.8.32 GMAC Stacked VLAN Register 42.8.33 GMAC Transmit PFC Pause Register 42.8.34 GMAC Specific Address 1 Mask Bottom Register 42.8.35 GMAC Specific Address Mask 1 Top Register 42.8.36 GMAC 1588 Timer Seconds Low Register 42.8.37 GMAC 1588 Timer Nanoseconds Register 42.8.38 GMAC 1588 Timer Adjust Register 42.8.39 GMAC 1588 Timer Increment Register 42.8.40 GMAC PTP Event Frame Transmitted Seconds Low Register 42.8.41 GMAC PTP Event Frame Transmitted Nanoseconds Register 42.8.42 GMAC PTP Event Frame Received Seconds Low Register 42.8.43 GMAC PTP Event Frame Received Nanoseconds Register 42.8.44 GMAC PTP Peer Event Frame Transmitted Seconds Low Register 42.8.45 GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 42.8.46 GMAC PTP Peer Event Frame Received Seconds Low Register 42.8.47 GMAC PTP Peer Event Frame Received Nanoseconds Register 43. Analog Front-End Controller (AFEC) 43.1 Description 43.2 Embedded Characteristics 43.3 Block Diagram 43.4 Signal Description 43.5 Product Dependencies 43.5.1 I/O Lines 43.5.2 Power Management 43.5.3 Interrupt Sources 43.5.4 Temperature Sensor 43.5.5 Timer Triggers 43.5.6 PWM Event Line 43.5.7 Fault Output 43.5.8 Conversion Performances 43.6 Functional Description 43.6.1 Analog Front-End Conversion 43.6.2 Conversion Reference 43.6.3 Conversion Resolution 43.6.4 Conversion Results 43.6.5 Conversion Triggers 43.6.6 Sleep Mode and Conversion Sequencer 43.6.7 Comparison Window 43.6.8 Differential Inputs 43.6.9 Input Gain and Offset 43.6.10 AFE Timings 43.6.11 Temperature Sensor 43.6.12 Enhanced Resolution Mode and Digital Averaging Function 43.6.13 Automatic Calibration 43.6.14 Buffer Structure 43.6.15 Fault Output 43.6.16 Register Write Protection 43.7 Analog Front-End Controller (AFEC) User Interface 43.7.1 AFEC Control Register 43.7.2 AFEC Mode Register 43.7.3 AFEC Extended Mode Register 43.7.4 AFEC Channel Sequence 1 Register 43.7.5 AFEC Channel Sequence 2 Register 43.7.6 AFEC Channel Enable Register 43.7.7 AFEC Channel Disable Register 43.7.8 AFEC Channel Status Register 43.7.9 AFEC Last Converted Data Register 43.7.10 AFEC Interrupt Enable Register 43.7.11 AFEC Interrupt Disable Register 43.7.12 AFEC Interrupt Mask Register 43.7.13 AFEC Interrupt Status Register 43.7.14 AFEC Overrun Status Register 43.7.15 AFEC Compare Window Register 43.7.16 AFEC Channel Gain Register 43.7.17 AFEC Channel Calibration DC Offset Register 43.7.18 AFEC Channel Differential Register 43.7.19 AFEC Channel Selection Register 43.7.20 AFEC Channel Data Register 43.7.21 AFEC Channel Offset Compensation Register 43.7.22 AFEC Temperature Sensor Mode Register 43.7.23 AFEC Temperature Compare Window Register 43.7.24 AFEC Analog Control Register 43.7.25 AFEC Write Protection Mode Register 43.7.26 AFEC Write Protection Status Register 44. Digital-to-Analog Converter Controller (DACC) 44.1 Description 44.2 Embedded Characteristics 44.3 Block Diagram 44.4 Signal Description 44.5 Product Dependencies 44.5.1 Power Management 44.5.2 Interrupt Sources 44.5.3 Conversion Performances 44.6 Functional Description 44.6.1 Digital-to-Analog Conversion 44.6.2 Conversion Results 44.6.3 Conversion Triggers 44.6.4 Conversion FIFO 44.6.5 Channel Selection 44.6.6 DACC Timings 44.6.7 Register Write Protection 44.7 Digital-to-Analog Converter Controller (DACC) User Interface 44.7.1 DACC Control Register 44.7.2 DACC Mode Register 44.7.3 DACC Channel Enable Register 44.7.4 DACC Channel Disable Register 44.7.5 DACC Channel Status Register 44.7.6 DACC Conversion Data Register 44.7.7 DACC Interrupt Enable Register 44.7.8 DACC Interrupt Disable Register 44.7.9 DACC Interrupt Mask Register 44.7.10 DACC Interrupt Status Register 44.7.11 DACC Analog Current Register 44.7.12 DACC Write Protection Mode Register 44.7.13 DACC Write Protection Status Register 45. Analog Comparator Controller (ACC) 45.1 Description 45.2 Embedded Characteristics 45.3 Block Diagram 45.4 Signal Description 45.5 Product Dependencies 45.5.1 I/O Lines 45.5.2 Power Management 45.5.3 Interrupt Sources 45.5.4 Fault Output 45.6 Functional Description 45.6.1 Description 45.6.2 Analog Settings 45.6.3 Output Masking Period 45.6.4 Fault Mode 45.6.5 Register Write Protection 45.7 Analog Comparator Controller (ACC) User Interface 45.7.1 ACC Control Register 45.7.2 ACC Mode Register 45.7.3 ACC Interrupt Enable Register 45.7.4 ACC Interrupt Disable Register 45.7.5 ACC Interrupt Mask Register 45.7.6 ACC Interrupt Status Register 45.7.7 ACC Analog Control Register 45.7.8 ACC Write Protection Mode Register 45.7.9 ACC Write Protection Status Register 46. SAM4E Electrical Characteristics 46.1 Absolute Maximum Ratings 46.2 DC Characteristics 46.3 Power Consumption 46.3.1 Backup Mode Current Consumption 46.3.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled 46.3.1.2 Configuration B: 32.768 kHz Crystal Oscillator Enabled 46.3.2 Sleep and Wait Mode Current Consumption 46.3.2.1 Sleep Mode 46.3.2.2 Wait Mode 46.3.3 Active Mode Power Consumption 46.3.3.1 SAM4E Active Power Consumption 46.3.3.2 SAM4E Active Total Power Consumption 46.3.4 Peripheral Power Consumption in Active Mode 46.4 Oscillator Characteristics 46.4.1 32 kHz RC Oscillator Characteristics 46.4.2 4/8/12 MHz RC Oscillators Characteristics 46.4.3 32.768 kHz Crystal Oscillator Characteristics 46.4.4 32.768 kHz Crystal Characteristics 46.4.5 3 to 20 MHz Crystal Oscillator Characteristics 46.4.6 3 to 20 MHz Crystal Characteristics 46.4.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode 46.4.8 Crystal Oscillator Design Considerations Information 46.4.8.1 Choosing a Crystal 46.4.8.2 Printed Circuit Board (PCB) 46.5 PLLA Characteristics 46.6 USB Transceiver Characteristics 46.6.1 Typical Connection 46.6.2 USB Electrical Characteristics 46.6.3 Switching Characteristics 46.7 12-bit AFE (Analog Front End) Characteristics 46.7.1 ADC Power Supply 46.7.1.1 ADC Bias Current 46.7.2 External Reference Voltage 46.7.3 ADC Timings 46.7.4 ADC Transfer Function 46.7.4.1 Differential Mode 46.7.4.2 Single-ended Mode 46.7.4.3 Example of LSB Computation 46.7.5 ADC Electrical Characteristics 46.7.5.1 Gain and Offset Errors Differential Mode Single-ended Mode 46.7.5.2 ADC Electrical Performances Single-ended Static Performances Single-ended Dynamic Performances Differential Static Performances Differential Dynamic Performances 10-bit ADC Mode Low Voltage Supply 46.7.5.3 ADC Channel Input Impedance Track and Hold Time versus Source Output Impedance 46.7.5.4 AFE DAC Offset Compensation 46.7.6 ADC Resolution with Averaging 46.7.6.1 Conditions @ 25°C with Gain = 1 46.7.6.2 Conditions @ 25°C with Gain = 4 46.8 12-bit DAC Characteristics 46.9 Analog Comparator Characteristics 46.10 Temperature Sensor 46.11 AC Characteristics 46.11.1 Master Clock Characteristics 46.11.2 I/O Characteristics 46.11.3 SPI Characteristics 46.11.3.1 Maximum SPI Frequency Master Write Mode Master Read Mode Slave Read Mode Slave Write Mode 46.11.3.2 SPI Timings 46.11.4 HSMCI Timings 46.11.5 SMC Timings 46.11.5.1 Read Timings 46.11.5.2 Write Timings 46.11.6 USART in SPI Mode Timings 46.11.6.1 USART SPI TImings 46.11.7 Two-wire Serial Interface Characteristics 46.11.8 Ethernet MAC (GMAC) Characteristics 46.11.8.1 Timing Conditions 46.11.8.2 Timing Constraints 46.11.8.3 MII Mode 46.11.9 Embedded Flash Characteristics 47. SAM4E Mechanical Characteristics 47.1 100-ball TFBGA Package Drawing 47.2 144-ball LFBGA Package Drawing 47.3 100-lead LQFP Package Drawing 47.4 144-lead LQFP Package Drawing 47.5 Soldering Profile 47.6 Packaging Resources 48. Marking 49. Ordering Information 50. Errata on SAM4E Devices 50.1 Errata SAM4E Rev. A Parts 50.1.1 Watchdog 50.1.1.1 Watchdog Not Stopped in Wait Mode 50.1.2 Brownout Detector 50.1.2.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected 50.1.3 Flash 50.1.3.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State 50.1.4 Floating Point Unit (FPU) 50.1.4.1 FPU: IXC flag interrupt 50.2 Errata SAM4E Rev.B Parts 50.2.1 Watchdog 50.2.1.1 Watchdog Not Stopped in Wait Mode 50.2.2 Brownout Detector 50.2.2.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected Table of Contents 51. Revision History