Datasheet PIC12(L)F1571/2 (Microchip) - 10

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PIC12(L)F1571/2 TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION Input Output Name Function Description Type Type
RA0/AN0/C1IN+/DACOUT/ RA0 General purpose I/O. TX
(2)
/CK
(2)
/CWG1B/PWM2/ AN0 ADC channel input. ICSPDAT/ICDDAT C1IN+ Comparator positive input. DACOUT Digital-to-Analog Converter output. TX USART asynchronous transmit.
(3) (4)
CK USART synchronous clock. CWG1B CWG complementary output. PWM2 PWM output. ICSPDAT ICSP™ data I/O. ICDDAT In-circuit debug data. RA1/AN1/VREF+/C1IN0-/RX
(2)
/ RA1 General purpose I/O. DT
(2)
/PWM1/ICSPCLK/ICDCLK AN1 ADC channel input. VREF+ ADC Voltage Reference input. C1IN0- Comparator negative input.
(3) (4)
RX USART asynchronous input. DT USART synchronous data. PWM1 PWM output. ICSPCLK ICSP programming clock. ICDCLK In-circuit debug clock. RA2/AN2/C1OUT/T0CKI/ RA2 General purpose I/O. CWG1FLT/CWG1A/PWM3/INT AN2 ADC channel input. C1OUT Comparator output. T0CKI Timer0 clock input.
(3) (4)
CWG1FLT Complementary Waveform Generator Fault input. CWG1A CWG complementary output. PWM3 PWM output. INT External interrupt. RA3/VPP/T1G
(1)
/MCLR RA3 General purpose input with IOC and WPU. VPP Programming voltage.
(3) (4)
T1G Timer1 gate input. MCLR Master Clear with internal pull-up. RA4/AN3/C1IN1-/T1G/TX
(1,2)
/ RA4 General purpose I/O. CK
(1,2)
/CWG1B
(1)
/PWM2
(1)
/ AN3 ADC channel input. CLKOUT C1IN1- Comparator negative input. T1G Timer1 gate input.
(3) (4)
TX USART asynchronous transmit. CK USART synchronous clock. CWG1B CWG complementary output. PWM2 PWM output. CLKOUT FOSC/4 output.
Legend:
AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels
Note 1:
Alternate pin function selected with the APFCON (Register 11-1) register.
2:
PIC12(L)F1572 only.
3:
Input type is selected by the port.
4:
Output type is selected by the port. DS40001723D-page 10  2013-2015 Microchip Technology Inc. Document Outline Description: Core Features: Memory: Operating Characteristics: eXtreme Low-Power (XLP) Features: Digital Peripherals: Device I/O Port Features: Analog Peripherals: Clocking Structure: PIC12(L)F1571/2 Family Types Pin Diagram – 8-Pin PDIP, SOIC, DFN, MSOP, UDFN TABLE 1: 8-Pin Allocation Table (PIC12(L)F1571/2) Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview TABLE 1-1: Device Peripheral Summary 1.1 Register and Bit Naming Conventions 1.1.1 Register Names 1.1.2 Bit Names 1.1.3 Register and Bit Naming Exceptions FIGURE 1-1: PIC12(L)F1571/2 Block Diagram TABLE 1-2: PIC12(L)F1571/2 Pinout Description 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization 3.2 High-Endurance Flash TABLE 3-1: Device Sizes and Addresses FIGURE 3-1: Program Memory Map and Stack for PIC12(L)F1571 FIGURE 3-2: Program Memory Map and Stack for PIC12(L)F1572 3.2.1 Reading Program Memory as Data EXAMPLE 3-1: RETLW Instruction EXAMPLE 3-2: Accessing Program Memory via FSR 3.3 Data Memory Organization 3.3.1 Core Registers TABLE 3-2: Core Registers Register 3-1: STATUS: STATUS Register 3.3.2 Special Function Register 3.3.3 General Purpose RAM 3.3.4 Common RAM 3.3.5 Device Memory Maps FIGURE 3-3: Banked Memory Partitioning TABLE 3-3: PIC12(L)F1571 Memory Map, Bank 0-7 TABLE 3-4: PIC12(L)F1572 Memory Map, Bank 0-7 TABLE 3-5: PIC12(L)F1571/2 Memory Map, Bank 8-23 TABLE 3-6: PIC12(L)F1571/2 Memory Map, Bank 24-31 TABLE 3-7: PIC12(L)F1571/2 Memory Map, Bank 27 TABLE 3-8: PIC12(L)F1571/2 Memory Map, Bank 31 3.3.6 Core Function Registers Summary TABLE 3-9: Core Function Registers Summary TABLE 3-10: Special Function Register Summary 3.4 PCL and PCLATH FIGURE 3-4: Loading of PC in Different Situations 3.4.1 Modifying PCL 3.4.2 Computed GOTO 3.4.3 Computed Function Calls 3.4.4 Branching 3.5 Stack 3.5.1 Accessing the Stack FIGURE 3-5: Accessing the Stack Example 1 FIGURE 3-6: Accessing the Stack Example 2 FIGURE 3-7: Accessing the Stack Example 3 FIGURE 3-8: Accessing the Stack Example 4 3.5.2 Overflow/Underflow Reset 3.6 Indirect Addressing FIGURE 3-9: Indirect Addressing 3.6.1 Traditional Data Memory FIGURE 3-10: Traditional Data Memory Map 3.6.2 Linear Data Memory FIGURE 3-11: Linear Data Memory Map 3.6.3 Program Flash Memory FIGURE 3-12: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words 4.2 Register Definitions: Configuration Words Register 4-1: CONFIG1: Configuration Word 1 Register 4-2: CONFIG2: Configuration Word 2 4.3 Code Protection 4.3.1 Program Memory Protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device ID Register 4-3: DEVICEID: Device ID Register(1) Register 4-4: REVISIONID: Revision ID Register(1) TABLE 4-1: Device ID Values 5.0 Oscillator Module 5.1 Overview FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram 5.2 Clock Source Types 5.2.1 External Clock Sources FIGURE 5-2: External Clock (EC) Mode Operation 5.2.2 Internal Clock Sources FIGURE 5-3: Internal Oscillator Switch Timing 5.3 Clock Switching 5.3.1 System Clock Select (SCSx) Bits 5.4 Clock Switching Before Sleep TABLE 5-1: Oscillator Switching Delays 5.5 Register Definitions: Oscillator Control Register 5-1: OSCCON: Oscillator Control Register Register 5-2: OSCSTAT: Oscillator Status Register Register 5-3: OSCTUNE: Oscillator Tuning Register TABLE 5-2: Summary of Registers Associated with Clock Sources TABLE 5-3: Summary of Configuration Word with Clock Sources 6.0 Resets FIGURE 6-1: Simplified Block Diagram of On-Chip Reset Circuit 6.1 Power-on Reset (POR) 6.1.1 Power-up Timer (PWRT) 6.2 Brown-out Reset (BOR) TABLE 6-1: BOR Operating Modes 6.2.1 BOR is Always On 6.2.2 BOR is Off in Sleep 6.2.3 BOR Controlled by Software FIGURE 6-2: Brown-out Situations 6.3 Register Definitions: BOR Control Register 6-1: BORCON: Brown-out Reset Control Register 6.4 Low-Power Brown-out Reset (LPBOR) 6.4.1 Enabling LPBOR 6.5 MCLR TABLE 6-2: MCLR Configuration 6.5.1 MCLR Enabled 6.5.2 MCLR Disabled 6.6 Watchdog Timer (WDT) Reset 6.7 RESET Instruction 6.8 Stack Overflow/Underflow Reset 6.9 Programming Mode Exit 6.10 Power-up Timer 6.11 Start-up Sequence FIGURE 6-3: Reset Start-up Sequence 6.12 Determining the Cause of a Reset TABLE 6-3: Reset Status Bits and Their Significance TABLE 6-4: Reset Condition for Special Registers 6.13 Power Control (PCON) Register 6.14 Register Definitions: Power Control Register 6-2: PCON: Power Control Register TABLE 6-5: Summary of Registers Associated with Resets TABLE 6-6: Summary of Configuration Word with Resets 7.0 Interrupts FIGURE 7-1: Interrupt Logic 7.1 Operation 7.2 Interrupt Latency FIGURE 7-2: Interrupt Latency FIGURE 7-3: INT Pin Interrupt Timing 7.3 Interrupts During Sleep 7.4 INT Pin 7.5 Automatic Context Saving 7.6 Register Definitions: Interrupt Control Register 7-1: INTCON: Interrupt Control Register Register 7-2: PIE1: Peripheral Interrupt Enable Register 1 Register 7-3: PIE2: Peripheral Interrupt Enable Register 2 Register 7-4: PIE3: Peripheral Interrupt Enable Register 3 Register 7-5: PIR1: Peripheral Interrupt Request Register 1 Register 7-6: PIR2: Peripheral Interrupt Request Register 2 Register 7-7: PIR3: Peripheral Interrupt Request Register 3 TABLE 7-1: Summary of Registers Associated with Interrupts 8.0 Power-Down Mode (Sleep) 8.1 Wake-up from Sleep 8.1.1 Wake-up Using Interrupts FIGURE 8-1: Wake-up from Sleep through Interrupt 8.2 Low-Power Sleep Mode 8.2.1 Sleep Current vs. Wake-up Time 8.2.2 Peripheral Usage in Sleep 8.3 Register Definitions: Voltage Regulator Control Register 8-1: VREGCON: Voltage Regulator Control Register(1) TABLE 8-1: Summary of Registers Associated with Power-Down Mode 9.0 Watchdog Timer (WDT) FIGURE 9-1: Watchdog Timer Block Diagram 9.1 Independent Clock Source 9.2 WDT Operating Modes 9.2.1 WDT Is Always On 9.2.2 WDT is Off in Sleep 9.2.3 WDT Controlled by Software TABLE 9-1: WDT Operating Modes 9.3 Time-out Period 9.4 Clearing the WDT 9.5 Operation During Sleep TABLE 9-2: WDT Clearing Conditions 9.6 Register Definitions: Watchdog Control Register 9-1: WDTCON: Watchdog Timer Control Register TABLE 9-3: Summary of Registers Associated with Watchdog Timer TABLE 9-4: Summary of Configuration Word with Watchdog Timer 10.0 Flash Program Memory Control 10.1 PMADRL and PMADRH Registers 10.1.1 PMCON1 and PMCON2 Registers 10.2 Flash Program Memory Overview TABLE 10-1: Flash Memory Organization by Device 10.2.1 Reading the Flash Program Memory FIGURE 10-1: Flash Program Memory Read Flowchart FIGURE 10-2: Flash Program Memory Read Cycle Execution EXAMPLE 10-1: Flash Program Memory Read 10.2.2 Flash Memory Unlock Sequence FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart 10.2.3 Erasing Flash Program Memory FIGURE 10-4: Flash Program Memory Erase Flowchart EXAMPLE 10-2: Erasing One Row of Program Memory 10.2.4 Writing to Flash Program Memory FIGURE 10-5: Block Writes to Flash Program Memory with 16 Write Latches FIGURE 10-6: Flash Program Memory Write Flowchart EXAMPLE 10-3: Writing to Flash Program Memory 10.3 Modifying Flash Program Memory FIGURE 10-7: Flash Program Memory Modify Flowchart 10.4 User ID, Device ID and Configuration Word Access TABLE 10-2: User ID, Device ID and Configuration Word Access (CFGS = 1) EXAMPLE 10-4: Configuration Word and Device ID Access 10.5 Write Verify FIGURE 10-8: Flash Program Memory Verify Flowchart 10.6 Register Definitions: Flash Program Memory Control Register 10-1: PMDATL: Program Memory Data Low Byte Register Register 10-2: PMDATH: Program Memory Data High Byte Register Register 10-3: PMADRL: Program Memory Address Low Byte Register Register 10-4: PMADRH: Program Memory Address High Byte Register Register 10-5: PMCON1: Program Memory Control 1 Register Register 10-6: PMCON2: Program Memory Control 2 Register TABLE 10-3: Summary of Registers Associated with Flash Program Memory TABLE 10-4: Summary of Configuration Word with Flash Program Memory 11.0 I/O Ports TABLE 11-1: Port Availability Per Device FIGURE 11-1: Generic I/O Port Operation 11.1 Alternate Pin Function 11.2 Register Definitions: Alternate Pin Function Control Register 11-1: APFCON: Alternate Pin Function Control Register 11.3 PORTA Registers 11.3.1 Data Register 11.3.2 Direction Control 11.3.3 Open-Drain Control 11.3.4 Slew Rate Control 11.3.5 Input Threshold Control 11.3.6 Analog Control EXAMPLE 11-1: Initializing PORTA 11.3.7 PORTA Functions and Output Priorities TABLE 11-2: PORTA Output Priority 11.4 Register Definitions: PORTA Register 11-2: PORTA: PORTA Register Register 11-3: TRISA: PORTA Tri-State Register Register 11-4: LATA: PORTA Data Latch Register Register 11-5: ANSELA: PORTA Analog Select Register Register 11-6: WPUA: Weak Pull-up PORTA Register Register 11-7: ODCONA: PORTA Open-Drain Control Register Register 11-8: SLRCONA: PORTA Slew Rate Control Register Register 11-9: INLVLA: PORTA Input Level Control Register TABLE 11-3: Summary of Registers Associated with PORTA TABLE 11-4: Summary of Configuration Word with PORTA 12.0 Interrupt-On-Change 12.1 Enabling the Module 12.2 Individual Pin Configuration 12.3 Interrupt Flags 12.4 Clearing Interrupt Flags EXAMPLE 12-1: Clearing Interrupt Flags (PORTA Example) 12.5 Operation in Sleep FIGURE 12-1: Interrupt-On-Change Block Diagram (PORTA Example) 12.6 Register Definitions: Interrupt-On-Change Control Register 12-1: IOCAP: Interrupt-On-Change PORTA Positive Edge Register Register 12-2: IOCAN: Interrupt-On-Change PORTA Negative Edge Register Register 12-3: IOCAF: Interrupt-On-Change PORTA Flag Register TABLE 12-1: Summary of Registers Associated with Interrupt-On-Change 13.0 Fixed Voltage Reference (FVR) 13.1 Independent Gain Amplifier 13.2 FVR Stabilization Period FIGURE 13-1: Voltage Reference Block Diagram TABLE 13-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 13.3 Register Definitions: FVR Control Register 13-1: FVRCON: Fixed Voltage Reference Control Register TABLE 13-2: Summary of Registers Associated with the Fixed Voltage Reference 14.0 Temperature Indicator Module 14.1 Circuit Operation EQUATION 14-1: Vout Ranges FIGURE 14-1: Temperature Circuit Diagram 14.2 Minimum Operating Vdd TABLE 14-1: Recommended Vdd vs. Range 14.3 Temperature Output 14.4 ADC Acquisition Time TABLE 14-2: Summary of Registers Associated with the Temperature Indicator 15.0 Analog-to-Digital Converter (ADC) Module FIGURE 15-1: ADC Block Diagram 15.1 ADC Configuration 15.1.1 Port Configuration 15.1.2 Channel Selection 15.1.3 ADC Voltage Reference 15.1.4 Conversion Clock TABLE 15-1: ADC Clock Period (Tad) vs. Device Operating Frequencies FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles 15.1.5 Interrupts 15.1.6 Result Formatting FIGURE 15-3: 10-Bit ADC Conversion Result Format 15.2 ADC Operation 15.2.1 Starting a Conversion 15.2.2 Completion of a Conversion 15.2.3 Terminating a Conversion 15.2.4 ADC Operation During Sleep 15.2.5 Auto-Conversion Trigger FIGURE 15-4: 16-Bit PWM Interrupt Block Diagram TABLE 15-2: Auto-Conversion Sources 15.2.6 ADC Conversion Procedure EXAMPLE 15-1: ADC Conversion 15.3 Register Definitions: ADC Control Register 15-1: ADCON0: ADC Control Register 0 Register 15-2: ADCON1: ADC Control Register 1 Register 15-3: ADCON2: ADC Control Register 2 Register 15-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 15-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 15-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 15-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 15.4 ADC Acquisition Requirements EQUATION 15-1: Acquisition Time Example FIGURE 15-5: Analog Input Model FIGURE 15-6: ADC Transfer Function TABLE 15-3: Summary of Registers Associated with ADC 16.0 5-Bit Digital-to-Analog Converter (DAC) Module FIGURE 16-1: Digital-to-Analog Converter Block Diagram 16.1 Output Voltage Selection 16.2 Ratiometric Output Level 16.3 DAC Voltage Reference Output 16.4 Operation During Sleep 16.5 Effects of a Reset EQUATION 16-1: DAC Output Voltage 16.6 Register Definitions: DAC Control Register 16-1: DACxCON0: DACx Voltage Reference Control Register 0 Register 16-2: DACxCON1: DACx Voltage Reference Control Register 1 TABLE 16-1: Summary of Registers Associated with the DAC Module 17.0 Comparator Module 17.1 Comparator Overview TABLE 17-1: Available Comparators FIGURE 17-1: Comparator Module Simplified Block Diagram FIGURE 17-2: Single Comparator 17.2 Comparator Control 17.2.1 Comparator Enable 17.2.2 Comparator Positive Input Selection 17.2.3 Comparator Negative Input Selection 17.2.4 Comparator Output Selection 17.2.5 Comparator Output Polarity TABLE 17-2: Comparator Output State vs. Input Conditions 17.2.6 Comparator Speed/Power Selection 17.3 Analog Input Connection Considerations FIGURE 17-3: Analog Input Model 17.4 Comparator Hysteresis 17.5 Timer1 Gate Operation 17.5.1 Comparator Output Synchronization 17.6 Comparator Interrupt 17.7 Comparator Response Time 17.8 Register Definitions: Comparator Control Register 17-1: CMxCON0: Comparator Cx Control Register 0 Register 17-2: CMxCON1: Comparator Cx Control Register 1 Register 17-3: CMOUT: Comparator Output Register TABLE 17-3: Summary of Registers Associated with Comparator Module 18.0 Timer0 Module 18.1 Timer0 Operation 18.1.1 8-Bit Timer Mode 18.1.2 8-Bit Counter Mode FIGURE 18-1: Timer0 Block Diagram 18.1.3 Software Programmable Prescaler 18.1.4 Timer0 Interrupt 18.1.5 8-Bit Counter Mode Synchronization 18.1.6 Operation During Sleep 18.2 Register Definitions: Option Register Register 18-1: OPTION_REG: Option Register TABLE 18-1: Summary of Registers Associated with Timer0 19.0 Timer1 Module with Gate Control FIGURE 19-1: Timer1 Block Diagram 19.1 Timer1 Operation TABLE 19-1: Timer1 Enable Selections 19.2 Clock Source Selection 19.2.1 Internal Clock Source 19.2.2 External Clock Source TABLE 19-2: Clock Source Selections 19.3 Timer1 Prescaler 19.4 Timer1 Operation in Asynchronous Counter Mode 19.4.1 Reading and Writing Timer1 in Asynchronous Counter Mode 19.5 Timer1 Gate 19.5.1 Timer1 Gate Enable TABLE 19-3: Timer1 Gate Enable Selections 19.5.2 Timer1 Gate Source Selection TABLE 19-4: Timer1 Gate Sources 19.5.3 Timer1 Gate Toggle Mode 19.5.4 Timer1 Gate Single-Pulse Mode 19.5.5 Timer1 Gate Value Status 19.5.6 Timer1 Gate Event Interrupt 19.6 Timer1 Interrupt 19.7 Timer1 Operation During Sleep 19.7.1 Alternate Pin Locations FIGURE 19-2: Timer1 Incrementing Edge FIGURE 19-3: Timer1 Gate Enable Mode FIGURE 19-4: Timer1 Gate Toggle Mode FIGURE 19-5: Timer1 Gate Single-Pulse Mode FIGURE 19-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 19.8 Register Definitions: Timer1 Control Register 19-1: T1CON: Timer1 Control Register Register 19-2: T1GCON: Timer1 Gate Control Register TABLE 19-5: Summary of Registers Associated with Timer1 20.0 Timer2 Module FIGURE 20-1: Timer2 Block Diagram FIGURE 20-2: Timer2 Timing Diagram 20.1 Timer2 Operation 20.2 Timer2 Interrupt 20.3 Timer2 Output FIGURE 20-3: T2_match Timing Diagram 20.4 Timer2 Operation During Sleep 20.5 Register Definitions: Timer2 Control Register 20-1: T2CON: Timer2 Control Register TABLE 20-1: Summary of Registers Associated with Timer2 21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 21-1: EUSART Transmit Block Diagram FIGURE 21-2: EUSART Receive Block Diagram 21.1 EUSART Asynchronous Mode 21.1.1 EUSART Asynchronous Transmitter FIGURE 21-3: Asynchronous Transmission FIGURE 21-4: Asynchronous Transmission (Back-to-Back) TABLE 21-1: Summary of Registers Associated with Asynchronous Transmission 21.1.2 EUSART Asynchronous Receiver FIGURE 21-5: Asynchronous Reception TABLE 21-2: Summary of Registers Associated with Asynchronous Reception 21.2 Clock Accuracy with Asynchronous Operation 21.3 Register Definitions: EUSART Control Register 21-1: TXSTA: Transmit Status and Control Register Register 21-2: RCSTA: Receive Status and Control Register Register 21-3: BAUDCON: Baud Rate Control Register 21.4 EUSART Baud Rate Generator (BRG) EXAMPLE 21-1: Calculating Baud Rate Error TABLE 21-3: Baud Rate Formulas TABLE 21-4: Summary of Registers Associated with the Baud Rate Generator TABLE 21-5: Baud Rates for Asynchronous Modes 21.4.1 Auto-Baud Detect TABLE 21-6: BRG Counter Clock Rates FIGURE 21-6: Automatic Baud Rate Calibration 21.4.2 Auto-Baud Overflow 21.4.3 Auto-Wake-up on Break FIGURE 21-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 21-8: Auto-Wake-up Bit (WUE) Timings During Sleep 21.4.4 Break Character Sequence 21.4.5 Receiving a Break Character FIGURE 21-9: Send Break Character Sequence 21.5 EUSART Synchronous Mode 21.5.1 Synchronous Master Mode FIGURE 21-10: Synchronous Transmission FIGURE 21-11: Synchronous Transmission (Through TXEN) TABLE 21-7: Summary of Registers Associated with Synchronous Master Transmission FIGURE 21-12: Synchronous Reception (Master Mode, SREN) TABLE 21-8: Summary of Registers Associated with Synchronous Master Reception 21.5.2 Synchronous Slave Mode TABLE 21-9: Summary of Registers Associated with Synchronous Slave Transmission TABLE 21-10: Summary of Registers Associated with Synchronous Slave Reception 22.0 16-Bit Pulse-Width Modulation (PWM) Module FIGURE 22-1: 16-Bit PWM Block Diagram FIGURE 22-2: Load Trigger Block Diagram 22.1 Fundamental Operation FIGURE 22-3: PWM Clock Source Block Diagram 22.1.1 PWMx Pin Configuration 22.1.2 PWMx Output Polarity 22.2 PWM Modes 22.2.1 Standard Mode EQUATION 22-1: PWM Period in Standard Mode EQUATION 22-2: PWM Duty Cycle in Standard Mode 22.2.2 Set On Match Mode 22.2.3 Toggle On Match Mode 22.2.4 Center-Aligned Mode EQUATION 22-3: PWM Period in Center-Aligned Mode EQUATION 22-4: PWM Duty Cycle in Center-Aligned Mode FIGURE 22-4: Standard PWM Mode Timing Diagram FIGURE 22-5: Set On Match PWM Mode Timing Diagram FIGURE 22-6: Toggle On Match PWM Mode Timing Diagram FIGURE 22-7: Center-Aligned PWM Mode Timing Diagram 22.3 Offset Modes 22.3.1 Independent Run Mode 22.3.2 Slave Run Mode with Sync Start 22.3.3 One-Shot Slave Mode with Sync Start 22.3.4 Continuous Run Slave Mode with Sync Start and Timer Reset 22.3.5 Offset Match in Center-Aligned Mode FIGURE 22-8: Independent Run Mode Timing Diagram FIGURE 22-9: Slave Run Mode with Sync Start Timing Diagram FIGURE 22-10: One-Shot Slave Run Mode with Sync Start Timing Diagram FIGURE 22-11: Continuous Slave Run Mode with Immediate Reset and Sync Start Timing Diagram FIGURE 22-12: Offset Match on Incrementing Timer Timing Diagram FIGURE 22-13: Offset Match on Decrementing Timer Timing Diagram 22.4 Reload Operation 22.4.1 Immediate Reload 22.4.2 Triggered Reload 22.5 Operation in Sleep Mode 22.6 Interrupts 22.7 Register Definitions: PWM Control TABLE 22-1: Bit Name Prefixes Register 22-1: PWMxCON: PWMx Control Register Register 22-2: PWMxINTE: PWMx Interrupt Enable Register Register 22-3: PWMxINTF: PWMx Interrupt Request Register Register 22-4: PWMxCLKCON: PWMx Clock Control Register Register 22-5: PWMxLDCON: PWMx Reload Trigger Source Select Register Register 22-6: PWMxOFCON: PWMx Offset Trigger Source Select Register Register 22-7: PWMxPHH: PWMx Phase Count High Register Register 22-8: PWMxPHL: PWMx Phase Count Low Register Register 22-9: PWMxDCH: PWMx Duty Cycle Count High Register Register 22-10: PWMxDCL: PWMx Duty Cycle Count Low Register Register 22-11: PWMxPRH: PWMx Period Count High Register Register 22-12: PWMxPRL: PWMx Period Count Low Register Register 22-13: PWMxOFH: PWMx Offset Count High Register Register 22-14: PWMxOFL: PWMx Offset Count Low Register Register 22-15: PWMxTMRH: PWMx Timer High Register Register 22-16: PWMxTMRL: PWMx Timer Low Register Register 22-17: PWMEN: PWMEN Bit Access Register Register 22-18: PWMLD: LD Bit Access Register Register 22-19: PWMOUT: PWMOUT Bit Access Register TABLE 22-2: Summary of Registers Associated with PWM TABLE 22-3: Summary of Configuration Word with Clock Sources 23.0 Complementary Waveform Generator (CWG) Module 23.1 Fundamental Operation 23.2 Clock Source 23.3 Selectable Input Sources TABLE 23-1: Selectable Input Sources 23.4 Output Control 23.4.1 Output Enables 23.4.2 Polarity Control FIGURE 23-1: Simplified CWG Block Diagram FIGURE 23-2: Typical CWG Operation with PWM1 (No Auto-Shutdown) 23.5 Dead-Band Control 23.6 Rising Edge Dead Band 23.7 Falling Edge Dead Band FIGURE 23-3: Dead-Band Operation, CWGxDBR = 01h, CWGxDBF = 02h FIGURE 23-4: Dead-Band Operation, CWGxDBR = 03h, CWGxDBF = 04h, Source Shorter than Dead Band 23.8 Dead-Band Uncertainty EQUATION 23-1: Dead-Band Uncertainty 23.9 Auto-Shutdown Control 23.9.1 Shutdown 23.10 Operation During Sleep 23.11 Configuring the CWG 23.11.1 Pin Override Levels 23.11.2 Auto-Shutdown Restart FIGURE 23-5: Shutdown Functionality, Auto-Restart Disabled (GxARSEN = 0, GxASDLA = 01, GxASDLB = 01) FIGURE 23-6: Shutdown Functionality, Auto-Restart Enabled (GxARSEN = 1, GxASDLA = 01, GxASDLB = 01) 23.12 Register Definitions: CWG Control Register 23-1: CWGxCON0: CWGx Control Register 0 Register 23-2: CWGxCON1: CWGx Control Register 1 Register 23-3: CWGXCON2: CWGx Control Register 2 Register 23-4: CWGxDBR: CWGx Complementary Waveform Generator Rising Dead-Band Count Register Register 23-5: CWGxDBF: CWGx Complementary Waveform Generator Falling Dead-Band Count Register TABLE 23-2: Summary of Registers Associated with CWG 24.0 In-Circuit Serial Programming™ (ICSP™) 24.1 High-Voltage Programming Entry Mode 24.2 Low-Voltage Programming Entry Mode 24.3 Common Programming Interfaces FIGURE 24-1: ICD RJ-11 Style Connector Interface FIGURE 24-2: PICkit™ Programmer Style Connector Interface FIGURE 24-3: Typical Connection for ICSP™ Programming 25.0 Instruction Set Summary 25.1 Read-Modify-Write Operations TABLE 25-1: Opcode Field Descriptions TABLE 25-2: Abbreviation Descriptions FIGURE 25-1: General Format for Instructions TABLE 25-3: Enhanced Mid-Range Instruction Set TABLE 25-3: Enhanced Mid-Range Instruction Set (Continued) 25.2 Instruction Descriptions 26.0 Electrical Specifications 26.1 Absolute Maximum Ratings(†) 26.2 Standard Operating Conditions FIGURE 26-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC12F1571/2 Only FIGURE 26-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC12LF1571/2 Only 26.3 DC Characteristics TABLE 26-1: Supply Voltage FIGURE 26-3: POR and POR Rearm with Slow Rising Vdd TABLE 26-2: Supply Current (Idd)(1,2) TABLE 26-3: Power-Down Currents (Ipd)(1,2) TABLE 26-4: I/O Ports TABLE 26-5: Memory Programming Specifications TABLE 26-6: Thermal Characteristics 26.4 AC Characteristics FIGURE 26-4: Load Conditions FIGURE 26-5: Clock Timing TABLE 26-7: Clock Oscillator Timing Requirements TABLE 26-8: Oscillator Parameters FIGURE 26-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 26-9: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V) FIGURE 26-7: CLKOUT and I/O Timing TABLE 26-10: CLKOUT and I/O Timing Parameters FIGURE 26-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 26-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Parameters FIGURE 26-9: Brown-out Reset Timing and Characteristics FIGURE 26-10: Timer0 and Timer1 External Clock Timings TABLE 26-12: Timer0 and Timer1 External Clock Requirements TABLE 26-13: Analog-to-Digital Converter (ADC) Characteristics(1,2,3) FIGURE 26-11: ADC Conversion Timing (ADC Clock Fosc-Based) FIGURE 26-12: ADC Conversion Timing (ADC Clock from FRC) TABLE 26-14: ADC Conversion Requirements TABLE 26-15: Comparator Specifications(1) TABLE 26-16: Digital-to-Analog Converter (DAC) Specifications(1) FIGURE 26-13: USART Synchronous Transmission (Master/Slave) Timing TABLE 26-17: USART Synchronous Transmission Requirements FIGURE 26-14: USART Synchronous Receive (Master/Slave) Timing TABLE 26-18: USART Synchronous Receive Requirements 27.0 DC and AC Characteristics Graphs and Charts FIGURE 27-1: Idd, EC Oscillator, Low-Power Mode, Fosc = 32 kHz, PIC12LF1571/2 Only FIGURE 27-2: Idd, EC Oscillator, Low-Power Mode, Fosc = 32 kHz, PIC12F1571/2 Only FIGURE 27-3: Idd, EC Oscillator, Low-Power Mode, Fosc = 500 kHz, PIC12LF1571/2 Only FIGURE 27-4: Idd, EC Oscillator, Low-Power Mode, Fosc = 500 kHz, PIC12F1571/2 Only FIGURE 27-5: Idd Typical, EC Oscillator, Medium Power Mode, PIC12LF1571/2 Only FIGURE 27-6: Idd Maximum, EC Oscillator, Medium Power Mode, PIC12LF1571/2 Only FIGURE 27-7: Idd Typical, EC Oscillator, Medium Power Mode, PIC12F1571/2 Only FIGURE 27-8: Idd Maximum, EC Oscillator, Medium Power Mode, PIC12F1571/2 Only FIGURE 27-9: Idd Typical, EC Oscillator, High-Power Mode, PIC12LF1571/2 Only FIGURE 27-10: Idd Maximum, EC Oscillator, High-Power Mode, PIC12LF1571/2 Only FIGURE 27-11: Idd Typical, EC Oscillator, High-Power Mode, PIC12F1571/2 Only FIGURE 27-12: Idd Maximum, EC Oscillator, High-Power Mode, PIC12F1571/2 Only FIGURE 27-13: Idd, LFINTOSC, Fosc = 31 kHz, PIC12LF1571/2 Only FIGURE 27-14: Idd, LFINTOSC, Fosc = 31 kHz, PIC12F1571/2 Only FIGURE 27-15: Idd, MFINTOSC, Fosc = 500 kHz, PIC12LF1571/2 Only FIGURE 27-16: Idd, MFINTOSC, Fosc = 500 kHz, PIC12F1571/2 Only FIGURE 27-17: Idd Typical, HFINTOSC, PIC12LF1571/2 Only FIGURE 27-18: Idd Maximum, HFINTOSC, PIC12LF1571/2 Only FIGURE 27-19: Idd Typical, HFINTOSC, PIC12F1571/2 Only FIGURE 27-20: Idd Maximum, HFINTOSC, PIC12F1571/2 Only FIGURE 27-21: Ipd Base, Low-Power Sleep Mode, PIC12LF1571/2 Only FIGURE 27-22: Ipd Base, Low-Power Sleep Mode, PIC12F1571/2 Only FIGURE 27-23: Ipd, Watchdog Timer (WDT), PIC12LF1571/2 Only FIGURE 27-24: Ipd, Watchdog Timer (WDT), PIC12F1571/2 Only FIGURE 27-25: Ipd, Fixed Voltage Reference (FVR), PIC12LF1571/2 Only FIGURE 27-26: Ipd, Fixed Voltage Reference (FVR), PIC12F1571/2 Only FIGURE 27-27: Ipd, Brown-out Reset (BOR), BORV = 1, PIC12LF1571/2 Only FIGURE 27-28: Ipd, Brown-out Reset (BOR), BORV = 1, PIC12F1571/2 Only FIGURE 27-29: Ipd, Low-Power Brown-out Reset (LPBOR = 0), PIC12LF1571/2 Only FIGURE 27-30: Ipd, Low-Power Brown-out Reset (LPBOR = 0), PIC12F1571/2 Only FIGURE 27-31: Ipd, ADC Non-Converting, PIC12LF1571/2 Only FIGURE 27-32: Ipd, ADC Non-Converting, PIC12F1571/2 Only FIGURE 27-33: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC12F1571/2 Only FIGURE 27-34: Ipd, Comparator, Normal Power Mode (CxSP = 1), PIC12LF1571/2 Only FIGURE 27-35: Ipd, Comparator, Normal Power Mode (CxSP = 1), PIC12F1571/2 Only FIGURE 27-36: Ipd, PWM, HFINTOSC Mode (16 MHz), PIC12LF1571/2 Only FIGURE 27-37: Ipd, PWM, HFINTOSC Mode (16 MHz), PIC12F1571/2 Only FIGURE 27-38: FVR Stabilization Period 28.0 Development Support 28.1 MPLAB X Integrated Development Environment Software 28.2 MPLAB XC Compilers 28.3 MPASM Assembler 28.4 MPLINK Object Linker/ MPLIB Object Librarian 28.5 MPLAB Assembler, Linker and Librarian for Various Device Families 28.6 MPLAB X SIM Software Simulator 28.7 MPLAB REAL ICE In-Circuit Emulator System 28.8 MPLAB ICD 3 In-Circuit Debugger System 28.9 PICkit 3 In-Circuit Debugger/ Programmer 28.10 MPLAB PM3 Device Programmer 28.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 28.12 Third-Party Development Tools 29.0 Packaging Information 29.1 Package Marking Information Package Marking Information (Continued) TABLE 29-1: 8-Lead 3x3x0.9 DFN (MF) Top Marking TABLE 29-2: 8-Lead 3x3x0.5 UDFN (RF) Top Marking 29.2 Package Details Appendix A: Data Sheet Revision History Revision A (10/2013) Revision B (2/2014) Revision C (8/2014) Revision D (8/2015) The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales