Datasheet PIC16F1574, PIC16F1575, PIC16F1578, PIC16F1579, PIC16LF1574, PIC16LF1575, PIC16LF1578, PIC16LF1579 (Microchip) - 9

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DS40001782C-page 9 Document Outline Description Core Features Memory Operating Characteristics eXtreme Low-Power (XLP) Features: Digital Peripherals Device I/O Port Features Analog Peripherals Clocking Structure TABLE 1: PIC12(L)F1571/2 and PIC16(L)F1574/5/8/9 Family Types TABLE 2: Packages FIGURE 1: 14-Pin PDIP, SOIC, TSSOP FIGURE 2: 16-Pin UQFN (4x4) FIGURE 3: 20-Pin PDIP, SOIC, SSOP FIGURE 4: 20-Pin UQFN (4x4) Pin Allocation Tables TABLE 3: 14/16-Pin Allocation Table (PIC16(L)F1574/5) TABLE 4: 20-Pin Allocation Table (PIC16(L)F1578/9) Most Current Data Sheet Errata Customer Notification System 14/20-Pin MCUs with High-Precision 16-Bit PWMs 1.0 Device Overview TABLE 1-1: Device Peripheral Summary 1.1 Register and Bit Naming Conventions FIGURE 1-1: PIC16(L)F1574/5/8/9 Block Diagram TABLE 1-2: PIC16(L)F1574/5 Pinout Description TABLE 1-3: PIC16(L)F1578/9 Pinout Description 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization 3.2 High-Endurance Flash TABLE 3-1: Device Sizes and Addresses FIGURE 3-1: Program Memory Map And Stack For PIC16(L)F1574/8 FIGURE 3-2: Program Memory Map And Stack For PIC16(L)F1575/9 EXAMPLE 3-1: RETLW Instruction EXAMPLE 3-2: Accessing Program Memory Via FSR 3.3 Data Memory Organization TABLE 3-2: Core Registers Register 3-1: STATUS: STATUS Register FIGURE 3-3: Banked Memory Partitioning TABLE 3-3: PIC16(L)F1574 Memory Map, Banks 0-7 TABLE 3-4: PIC16(L)F1575 Memory Map, Banks 0-7 TABLE 3-5: PIC16(L)F1578 Memory Map, Banks 0-7 TABLE 3-6: PIC16(L)F1579 Memory Map, Banks 0-7 TABLE 3-7: PIC16(L)F1574/8 Memory Map, Banks 8-15 TABLE 3-8: PIC16(L)F1575/9 Memory Map, Banks 8-15 TABLE 3-9: PIC16(L)F1574/5/8/9 Memory Map, Banks 16-23 TABLE 3-10: PIC16(L)F1574/5/8/9 Memory Map, Banks 24-31 TABLE 3-11: PIC16(L)F1574/5/8/9 Memory Map, Bank 27 TABLE 3-12: PIC16(L)F1574/5/8/9 Memory Map, Bank 28-29 TABLE 3-13: PIC16(L)F1574/5/8/9 Memory Map, Bank 31 TABLE 3-14: Core Function Registers Summary TABLE 3-15: Special Function Register Summary 3.4 PCL and PCLATH FIGURE 3-4: Loading of PC in Different Situations 3.5 Stack FIGURE 3-5: Accessing the Stack Example 1 FIGURE 3-6: Accessing the Stack Example 2 FIGURE 3-7: Accessing the Stack Example 3 FIGURE 3-8: Accessing the Stack Example 4 3.6 Indirect Addressing FIGURE 3-9: Indirect Addressing FIGURE 3-10: Traditional Data Memory Map FIGURE 3-11: Linear Data Memory Map FIGURE 3-12: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words 4.2 Register Definitions: Configuration Words Register 4-1: Configuration Word 1 Register 4-2: Configuration Word 2 4.3 Code Protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device ID Register 4-3: DEVICEID: Device ID Register(1) Register 4-4: REVISIONID: Revision ID Register(1) TABLE 4-1: Device ID Values 5.0 Oscillator Module 5.1 Overview FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram 5.2 Clock Source Types FIGURE 5-2: External Clock (EC) Mode Operation FIGURE 5-3: Internal Oscillator Switch Timing 5.3 Clock Switching 5.4 Clock Switching Before Sleep TABLE 5-1: Oscillator Switching Delays 5.5 Register Definitions: Oscillator Control Register 5-1: OSCCON: Oscillator Control Register Register 5-2: OSCSTAT: Oscillator Status Register Register 5-3: OSCTUNE: Oscillator Tuning Register TABLE 5-2: Summary of Registers Associated with Clock Sources TABLE 5-3: Summary of Configuration Word with Clock Sources 6.0 Resets FIGURE 6-1: Simplified Block Diagram of On-Chip Reset Circuit 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) TABLE 6-1: BOR Operating Modes FIGURE 6-2: Brown-out Situations 6.3 Register Definitions: BOR Control Register 6-1: BORCON: Brown-out Reset Control Register 6.4 Low-Power Brown-Out Reset (LPBOR) 6.5 MCLR TABLE 6-2: MCLR Configuration 6.6 Watchdog Timer (WDT) Reset 6.7 RESET Instruction 6.8 Stack Overflow/Underflow Reset 6.9 Programming Mode Exit 6.10 Power-Up Timer 6.11 Start-up Sequence FIGURE 6-3: Reset Start-up Sequence 6.12 Determining the Cause of a Reset TABLE 6-3: Reset Status Bits and Their Significance TABLE 6-4: Reset Condition for Special Registers 6.13 Power Control (PCON) Register 6.14 Register Definitions: Power Control Register 6-2: PCON: Power Control Register TABLE 6-5: Summary of Registers Associated with Resets TABLE 6-6: Summary of Configuration Word with Resets 7.0 Interrupts FIGURE 7-1: Interrupt Logic 7.1 Operation 7.2 Interrupt Latency FIGURE 7-2: Interrupt Latency FIGURE 7-3: INT Pin Interrupt Timing 7.3 Interrupts During Sleep 7.4 INT Pin 7.5 Automatic Context Saving 7.6 Register Definitions: Interrupt Control Register 7-1: INTCON: Interrupt Control Register Register 7-2: PIE1: Peripheral Interrupt Enable Register 1 Register 7-3: PIE2: Peripheral Interrupt Enable Register 2 Register 7-4: PIE3: Peripheral Interrupt Enable Register 3 Register 7-5: PIR1: Peripheral Interrupt Request Register 1 Register 7-6: PIR2: Peripheral Interrupt Request Register 2 Register 7-7: PIR3: Peripheral Interrupt Request Register 3 TABLE 7-1: Summary of Registers Associated with Interrupts 8.0 Power-Down Mode (Sleep) 8.1 Wake-up from Sleep FIGURE 8-1: Wake-up from Sleep through Interrupt 8.2 Low-Power Sleep Mode 8.3 Register Definitions: Voltage Regulator Control Register 8-1: VREGCON: Voltage Regulator Control Register(1) TABLE 8-1: Summary of Registers Associated with Power-Down Mode 9.0 Watchdog Timer (WDT) FIGURE 9-1: Watchdog Timer Block Diagram 9.1 Independent Clock Source 9.2 WDT Operating Modes TABLE 9-1: WDT Operating Modes 9.3 Time-Out Period 9.4 Clearing the WDT 9.5 Operation During Sleep TABLE 9-2: WDT Clearing Conditions 9.6 Register Definitions: Watchdog Control Register 9-1: WDTCON: Watchdog Timer Control Register TABLE 9-3: Summary of Registers Associated with Watchdog Timer TABLE 9-4: Summary of Configuration Word with Watchdog Timer 10.0 Flash Program Memory Control 10.1 PMADRL and PMADRH Registers 10.2 Flash Program Memory Overview TABLE 10-1: Flash Memory Organization by Device FIGURE 10-1: Flash Program Memory Read Flowchart FIGURE 10-2: Flash Program Memory Read Cycle Execution EXAMPLE 10-1: Flash Program Memory Read FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart FIGURE 10-4: Flash Program Memory Erase Flowchart EXAMPLE 10-2: Erasing One Row of Program Memory FIGURE 10-5: Block Writes to Flash Program Memory with 32 Write Latches FIGURE 10-6: Flash Program Memory Write Flowchart EXAMPLE 10-3: Writing to Flash Program Memory 10.3 Modifying Flash Program Memory FIGURE 10-7: Flash Program Memory Modify Flowchart 10.4 User ID, Device ID and Configuration Word Access TABLE 10-2: User ID, Device ID and Configuration Word Access (CFGS = 1) EXAMPLE 10-4: Configuration Word and Device ID Access 10.5 Write Verify FIGURE 10-8: Flash Program Memory Verify Flowchart 10.6 Register Definitions: Flash Program Memory Control Register 10-1: PMDATL: Program Memory Data Low Byte Register Register 10-2: PMDATH: Program Memory Data High Byte Register Register 10-3: PMADRL: Program Memory Address Low Byte Register Register 10-4: PMADRH: Program Memory Address High Byte Register Register 10-5: PMCON1: Program Memory Control 1 Register Register 10-6: PMCON2: Program Memory Control 2 Register TABLE 10-3: Summary of Registers Associated with Flash Program Memory TABLE 10-4: Summary of Configuration Word with Flash Program Memory 11.0 I/O Ports TABLE 11-1: Port Availability Per Device FIGURE 11-1: Generic I/O Port Operation 11.1 PORTA Registers EXAMPLE 11-1: Initializing PORTA 11.2 Register Definitions: PORTA Register 11-1: PORTA: PORTA Register Register 11-2: TRISA: PORTA Tri-State Register Register 11-3: LATA: PORTA Data Latch Register Register 11-4: ANSELA: PORTA Analog Select Register Register 11-5: WPUA: Weak Pull-Up PORTA Register Register 11-6: ODCONA: PORTA Open-Drain Control Register Register 11-7: SLRCONA: PORTA Slew Rate Control Register Register 11-8: INLVLA: PORTA Input Level Control Register TABLE 11-2: Summary of Registers Associated with PORTA TABLE 11-3: Summary of Configuration Word with PORTA 11.3 PORTB Registers (PIC16(L)F1578/9 only) 11.4 Register Definitions: PORTB Register 11-9: PORTB: PORTB Register Register 11-10: TRISB: PORTB Tri-State Register Register 11-11: LATB: PORTB Data Latch Register Register 11-12: ANSELB: PORTB Analog Select Register Register 11-13: WPUB: Weak Pull-Up PORTB Register Register 11-14: ODCONB: PORTB Open Drain Control Register Register 11-15: SLRCONB: PORTB Slew Rate Control Register Register 11-16: INLVLB: PORTB Input Level Control Register TABLE 11-4: Summary of Registers Associated with PORTB 11.5 PORTC Registers 11.6 Register Definitions: PORTC Register 11-17: PORTC: PORTC Register Register 11-18: TRISC: PORTC Tri-State Register Register 11-19: LATC: PORTC Data Latch Register Register 11-20: ANSELC: PORTC Analog Select Register Register 11-21: WPUC: Weak Pull-Up PORTC Register Register 11-22: ODCONC: PORTC Open Drain Control Register Register 11-23: SLRCONC: PORTC Slew Rate Control Register Register 11-24: INLVLC: PORTC Input Level Control Register TABLE 11-5: Summary of Registers Associated with PORTC 12.0 Peripheral Pin Select (PPS) Module 12.1 PPS Inputs 12.2 PPS Outputs FIGURE 12-1: Simplified PPS Block Diagram 12.3 Bidirectional Pins 12.4 PPS Lock EXAMPLE 12-1: PPS Lock/Unlock Sequence 12.5 PPS Permanent Lock 12.6 Operation During Sleep 12.7 Effects of a Reset 12.8 Register Definitions: PPS Input Selection Register 12-1: xxxPPS: Peripheral xxx input Selection Register 12-2: RxyPPS: Pin Rxy Output Source Selection Register Register 12-3: PPSLOCK: PPS Lock Register TABLE 12-1: PPS Input register reset values TABLE 12-2: Available PORTS for output by peripheral(2) TABLE 12-3: Summary of Registers Associated with the PPS Module 13.0 Interrupt-On-Change 13.1 Enabling the Module 13.2 Individual Pin Configuration 13.3 Interrupt Flags 13.4 Clearing Interrupt Flags EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example) 13.5 Operation in Sleep FIGURE 13-1: Interrupt-On-Change Block Diagram (PORTA Example) 13.6 Register Definitions: Interrupt-on-Change Control Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 13-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register(1) Register 13-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register(1) Register 13-6: IOCBF: Interrupt-on-Change PORTB Flag Register(1) Register 13-7: IOCCP: Interrupt-on-Change PORTC Positive Edge Register(1) Register 13-8: IOCCN: Interrupt-on-Change PORTC Negative Edge Register(1) Register 13-9: IOCCF: Interrupt-on-Change PORTC Flag Register(1) TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change 14.0 Fixed Voltage Reference (FVR) 14.1 Independent Gain Amplifier 14.2 FVR Stabilization Period FIGURE 14-1: Voltage Reference Block Diagram TABLE 14-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 14.3 Register Definitions: FVR Control Register 14-1: FVRCON: Fixed Voltage Reference Control Register TABLE 14-2: Summary of Registers Associated with the Fixed Voltage Reference 15.0 Temperature Indicator Module 15.1 Circuit Operation EQUATION 15-1: Vout Ranges FIGURE 15-1: Temperature Circuit Diagram 15.2 Minimum Operating Vdd TABLE 15-1: Recommended Vdd vs. Range 15.3 Temperature Output 15.4 ADC Acquisition Time TABLE 15-2: Summary of Registers Associated with the Temperature Indicator 16.0 Analog-to-Digital Converter (ADC) Module FIGURE 16-1: ADC Block Diagram 16.1 ADC Configuration TABLE 16-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 16-2: Analog-to-Digital Conversion Tad Cycles FIGURE 16-3: 10-Bit ADC Conversion Result Format 16.2 ADC Operation FIGURE 16-4: 16-bit PWM Interrupt Block Diagram TABLE 16-2: Auto-Conversion Sources EXAMPLE 16-1: ADC Conversion 16.3 Register Definitions: ADC Control Register 16-1: ADCON0: ADC Control Register 0 Register 16-2: ADCON1: ADC Control Register 1 Register 16-3: ADCON2: ADC Control Register 2 Register 16-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 16-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 16-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 16-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 16.4 ADC Acquisition Requirements EQUATION 16-1: Acquisition Time Example FIGURE 16-5: Analog Input Model FIGURE 16-6: ADC Transfer Function TABLE 16-3: Summary of Registers Associated with ADC 17.0 5-Bit Digital-to-Analog Converter (DAC) Module FIGURE 17-1: Digital-to-Analog Converter Block Diagram 17.1 Output Voltage Selection 17.2 Ratiometric Output Level 17.3 DAC Voltage Reference Output 17.4 Operation During Sleep 17.5 Effects of a Reset EQUATION 17-1: DAC Output Voltage 17.6 Register Definitions: DAC Control Register 17-1: DACCON0: Voltage Reference Control Register 0 Register 17-2: DACCON1: Voltage Reference Control Register 1 TABLE 17-1: Summary of Registers Associated with the DAC Module 18.0 Comparator Module 18.1 Comparator Overview TABLE 18-1: Available Comparators FIGURE 18-1: Comparator Module Simplified Block Diagram FIGURE 18-2: Single Comparator 18.2 Comparator Control TABLE 18-2: Comparator Output State vs. Input Conditions 18.3 Analog Input Connection Considerations FIGURE 18-3: Analog Input Model 18.4 Comparator Hysteresis 18.5 Timer1 Gate Operation 18.6 Comparator Interrupt 18.7 Comparator Response Time 18.8 Register Definitions: Comparator Control Register 18-1: CMxCON0: Comparator Cx Control Register 0 Register 18-2: CMxCON1: Comparator Cx Control Register 1 Register 18-3: CMOUT: Comparator Output Register TABLE 18-3: Summary of Registers Associated with Comparator Module 19.0 Timer0 Module 19.1 Timer0 Operation FIGURE 19-1: Timer0 Block Diagram 19.2 Register Definitions: Option Register Register 19-1: OPTION_REG: OPTION Register TABLE 19-1: Summary of Registers Associated with Timer0 20.0 Timer1 Module with Gate Control FIGURE 20-1: Timer1 Block Diagram 20.1 Timer1 Operation TABLE 20-1: Timer1 Enable Selections 20.2 Clock Source Selection TABLE 20-2: Clock Source Selections 20.3 Timer1 Prescaler 20.4 Timer1 Operation in Asynchronous Counter Mode 20.5 Timer1 Gate TABLE 20-3: Timer1 Gate Enable Selections TABLE 20-4: Timer1 Gate Sources 20.6 Timer1 Interrupt 20.7 Timer1 Operation During Sleep FIGURE 20-2: Timer1 Incrementing Edge FIGURE 20-3: Timer1 Gate Enable Mode FIGURE 20-4: Timer1 Gate Toggle Mode FIGURE 20-5: Timer1 Gate Single-Pulse Mode FIGURE 20-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 20.8 Register Definitions: Timer1 Control Register 20-1: T1CON: Timer1 Control Register Register 20-2: T1GCON: Timer1 Gate Control Register TABLE 20-5: Summary of Registers Associated with Timer1 21.0 Timer2 Module FIGURE 21-1: Timer2 Block Diagram FIGURE 21-2: Timer2 Timing Diagram 21.1 Timer2 Operation 21.2 Timer2 Interrupt 21.3 Timer2 Output FIGURE 21-3: T2_match Timing Diagram 21.4 Timer2 Operation During Sleep 21.5 Register Definitions: Timer2 Control Register 21-1: T2CON: Timer2 Control Register TABLE 21-1: Summary of Registers Associated With Timer2 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 22-1: EUSART Transmit Block Diagram FIGURE 22-2: EUSART Receive Block Diagram 22.1 EUSART Asynchronous Mode FIGURE 22-3: Asynchronous Transmission FIGURE 22-4: Asynchronous Transmission (Back-to-Back) TABLE 22-1: Summary of Registers Associated with Asynchronous Transmission FIGURE 22-5: Asynchronous Reception TABLE 22-2: Summary of Registers Associated with Asynchronous Reception 22.2 Clock Accuracy with Asynchronous Operation 22.3 Register Definitions: EUSART Control Register 22-1: TXSTA: Transmit Status and Control Register Register 22-2: RCSTA: Receive Status and Control Register Register 22-3: BAUDCON: Baud Rate Control Register 22.4 EUSART Baud Rate Generator (BRG) EXAMPLE 22-1: Calculating Baud Rate Error TABLE 22-3: Baud Rate Formulas TABLE 22-4: Summary of Registers Associated with the Baud Rate Generator TABLE 22-5: BAUD Rates for Asynchronous Modes TABLE 22-6: BRG Counter Clock Rates FIGURE 22-6: Automatic Baud Rate Calibration FIGURE 22-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 22-8: Auto-Wake-up Bit (WUE) Timings During Sleep FIGURE 22-9: Send Break Character Sequence 22.5 EUSART Synchronous Mode FIGURE 22-10: Synchronous Transmission FIGURE 22-11: Synchronous Transmission (Through TXEN) TABLE 22-7: Summary of Registers Associated with Synchronous Master Transmission FIGURE 22-12: Synchronous Reception (Master Mode, SREN) TABLE 22-8: Summary of Registers Associated with Synchronous Master Reception TABLE 22-9: Summary of Registers Associated with Synchronous Slave Transmission TABLE 22-10: Summary of Registers Associated with Synchronous Slave Reception 23.0 16-bit Pulse-Width Modulation (PWM) Module FIGURE 23-1: 16-bit PWM Block Diagram FIGURE 23-2: Load Trigger Block Diagram 23.1 Fundamental Operation FIGURE 23-3: PWM Clock Source Block Diagram 23.2 PWM Modes EQUATION 23-1: PWM Period in Standard Mode EQUATION 23-2: PWM Duty Cycle in Standard Mode EQUATION 23-3: PWM Period in Center-Aligned Mode EQUATION 23-4: PWM Duty Cycle in Center-Aligned Mode FIGURE 23-4: Standard PWM Mode Timing Diagram FIGURE 23-5: Set On Match PWM Mode Timing Diagram FIGURE 23-6: Toggle-on Match PWM Mode Timing Diagram FIGURE 23-7: Center-Aligned PWM Mode Timing Diagram 23.3 Offset Modes FIGURE 23-8: Independent Run Mode Timing Diagram FIGURE 23-9: Slave Run Mode with Sync Start Timing Diagram FIGURE 23-10: One-Shot Slave Run Mode with Sync Start Timing Diagram FIGURE 23-11: Continuous Slave Run Mode with Immediate Reset and Sync Start Timing Diagram FIGURE 23-12: Offset Match on Incrementing Timer Timing Diagram FIGURE 23-13: Offset Match on Decrementing Timer Timing Diagram 23.4 Reload Operation 23.5 Operation in Sleep Mode 23.6 Interrupts 23.7 Register Definitions: PWM Control TABLE 23-1: Register 23-1: PWMxCON: PWM Control Register Register 23-2: PWMxINTE: PWM Interrupt ENABLE Register Register 23-3: PWMxINTF: PWM Interrupt Request Register Register 23-4: PWMxCLKCON: PWM Clock Control Register Register 23-5: PWMxLDCON: PWM Reload Trigger Source Select Register Register 23-6: PWMxOFCON: PWM Offset Trigger Source Select Register Register 23-7: PWMxPHH: PWMx Phase Count High Register Register 23-8: PWMxPHL: PWMx Phase Count Low Register Register 23-9: PWMxDCH: PWMx Duty Cycle Count High Register Register 23-10: PWMxDCL: PWMx Duty Cycle Count Low Register Register 23-11: PWMxPRH: PWMx Period Count High Register Register 23-12: PWMxPRL: PWMx Period Count Low Register Register 23-13: PWMxOFH: PWMx Offset Count High Register Register 23-14: PWMxOFL: PWMx Offset Count Low Register Register 23-15: PWMxTMRH: PWMx Timer High Register Register 23-16: PWMxTMRL: PWMx Timer Low Register Register 23-17: PWMEN: PWMEN Bit Access Register Register 23-18: PWMLD: LD Bit Access Register Register 23-19: PWMOUT: PWMOUT Bit Access Register TABLE 23-2: Summary of Registers Associated with PWM TABLE 23-2: Summary of Registers Associated with PWM (Continued) TABLE 23-3: Summary of Configuration Word with Clock Sources 24.0 Complementary Waveform Generator (CWG) Module 24.1 Fundamental Operation 24.2 Clock Source 24.3 Selectable Input Sources TABLE 24-1: Selectable Input Sources 24.4 Output Control FIGURE 24-1: Simplified CWG Block Diagram FIGURE 24-2: Typical CWG Operation with PWM1 (No Auto-shutdown) 24.5 Dead-Band Control 24.6 Rising Edge Dead Band 24.7 Falling Edge Dead Band FIGURE 24-3: Dead-Band Operation, CWGxDBR = 01H, CWGxDBF = 02H FIGURE 24-4: Dead-Band Operation, CWGxDBR = 03H, CWGxDBF = 04H, Source Shorter Than Dead Band 24.8 Dead-Band Uncertainty EQUATION 24-1: Dead-Band Uncertainty 24.9 Auto-Shutdown Control 24.10 Operation During Sleep 24.11 Configuring the CWG FIGURE 24-5: Shutdown Functionality, Auto-Restart Disabled (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01) FIGURE 24-6: Shutdown Functionality, Auto-Restart Enabled (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01) 24.12 Register Definitions: CWG Control Register 24-1: CWGxCON0: CWG Control Register 0 Register 24-2: CWGxCON1: CWG Control Register 1 Register 24-3: CWGXCON2: CWG Control Register 2 Register 24-4: CWGxDBR: Complementary Waveform Generator (CWGx) Rising Dead-Band Count Register Register 24-5: CWGxdbf: Complementary Waveform Generator (CWGx) Falling Dead-Band Count Register TABLE 24-2: Summary of Registers Associated with CWG 25.0 In-Circuit Serial Programming™ (ICSP™) 25.1 High-Voltage Programming Entry Mode 25.2 Low-Voltage Programming Entry Mode 25.3 Common Programming Interfaces FIGURE 25-1: ICD RJ-11 Style Connector Interface FIGURE 25-2: PICkit™ Programmer Style Connector Interface FIGURE 25-3: Typical connection for ICSP™ Programming 26.0 Instruction Set Summary 26.1 Read-Modify-Write Operations TABLE 26-1: Opcode Field Descriptions TABLE 26-2: Abbreviation Descriptions FIGURE 26-1: General Format for Instructions TABLE 26-3: Enhanced Mid-Range Instruction Set TABLE 26-3: Enhanced Mid-Range Instruction Set (Continued) 26.2 Instruction Descriptions 27.0 Electrical Specifications 27.1 Absolute Maximum Ratings(†) 27.2 Standard Operating Conditions FIGURE 27-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F1574/5/8/9 only FIGURE 27-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF1574/5/8/9 only 27.3 DC Characteristics TABLE 27-1: Supply Voltage FIGURE 27-3: POR and POR Rearm with Slow Rising Vdd TABLE 27-2: Supply Current (Idd)(1,2) TABLE 27-3: Power-Down Currents (Ipd)(1,2) TABLE 27-4: I/O Ports TABLE 27-5: Memory Programming Specifications TABLE 27-6: Thermal Characteristics 27.4 AC Characteristics FIGURE 27-4: Load Conditions FIGURE 27-5: Clock Timing TABLE 27-7: Clock Oscillator Timing Requirements TABLE 27-8: Oscillator Parameters FIGURE 27-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 27-9: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V) FIGURE 27-7: CLKOUT and I/O Timing TABLE 27-10: CLKOUT and I/O Timing Parameters FIGURE 27-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 27-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters FIGURE 27-9: Brown-Out Reset Timing and Characteristics FIGURE 27-10: Timer0 and Timer1 External Clock Timings TABLE 27-12: Timer0 and Timer1 External Clock Requirements TABLE 27-13: Analog-to-Digital Converter (ADC) Characteristics(1,2,3) FIGURE 27-11: ADC Conversion Timing (ADC Clock Fosc-based) FIGURE 27-12: ADC Conversion Timing (ADC Clock from FRC) TABLE 27-14: ADC Conversion Requirements TABLE 27-15: Comparator Specifications(1) TABLE 27-16: Digital-to-Analog Converter (DAC) Specifications(1) FIGURE 27-13: USART Synchronous Transmission (Master/Slave) Timing TABLE 27-17: USART Synchronous Transmission Requirements FIGURE 27-14: USART Synchronous Receive (Master/Slave) Timing TABLE 27-18: USART Synchronous Receive Requirements 28.0 DC and AC Characteristics Graphs and Charts 29.0 Development Support 29.1 MPLAB X Integrated Development Environment Software 29.2 MPLAB XC Compilers 29.3 MPASM Assembler 29.4 MPLINK Object Linker/ MPLIB Object Librarian 29.5 MPLAB Assembler, Linker and Librarian for Various Device Families 29.6 MPLAB X SIM Software Simulator 29.7 MPLAB REAL ICE In-Circuit Emulator System 29.8 MPLAB ICD 3 In-Circuit Debugger System 29.9 PICkit 3 In-Circuit Debugger/ Programmer 29.10 MPLAB PM3 Device Programmer 29.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 29.12 Third-Party Development Tools 30.0 Packaging Information 30.1 Package Marking Information Package Marking Information (Continued) Package Marking Information (Continued) 30.2 Package Details Appendix A: Data Sheet Revision History Revision A (2/2015) Revision B (09/2015) Revision C (01/2016) The Microchip Website Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales and Service