Datasheet PIC16F1703, PIC16F1707, PIC16LF1703, PIC16LF1707 (Microchip) - 4

PIC16(L)F1703/7 FIGURE 3: 20-PIN PACKAGE DIAGRAM FOR PIC16(L)F1707 PDIP, SOIC, SSOP
VDD 20 VSS 1 RA5 2 19 RA0/ICSPDAT RA4 3 18 RA1/ICSPCLK VPP/MCLR/RA3 4 17 RA2
707 1
RC5 5 16 RC0
)F
RC4 6 15 RC1
6(L 1
RC3 7 14 RC2
IC P
RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6
FIGURE 4: 20-PIN PACKAGE DIAGRAM FOR PIC16(L)F1707 QFN
T DA SP 4 5 /IC DD SS RA RA V V RA0 20 19 18 17 16 VPP/MCLR/RA3 1 15 RA1/ICSPCLK RC5 2 14 RA2 RC4 3
PIC16(L)F1707
13 RC0 RC3 4 12 RC1 RC6 5 11 RC2 6 7 8 9 10 RC7 RB7 RB6 RB5 RB4 DS40001722C-page 4  2013-2015 Microchip Technology Inc. Document Outline Core Features Memory Operating Characteristics Digital Peripherals eXtreme Low-Power (XLP) Features Intelligent Analog Peripherals Clocking Structure Programming/Debug Features Pin Diagrams Table of Contents 1.0 Device Overview TABLE 1-1: Device Peripheral Summary FIGURE 1-1: PIC16(L)F1703/7 Block Diagram TABLE 1-2: PIC16(L)F1703 PinOut Description TABLE 1-3: PIC16(L)F1707 PinOut Description 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization 3.2 High-Endurance Flash TABLE 3-1: Device Sizes and Addresses FIGURE 3-1: Program Memory Map and Stack for PIC16(L)F1703/7 3.2.1 Reading Program Memory as Data EXAMPLE 3-1: RETLW Instruction EXAMPLE 3-2: Accessing Program Memory Via FSR 3.3 Data Memory Organization 3.3.1 Core Registers TABLE 3-2: Core Registers 3.4 Register Definitions: Status Register 3-1: STATUS: STATUS Register 3.4.1 Special Function Register 3.4.2 General Purpose RAM 3.4.3 Common RAM FIGURE 3-2: Banked Memory Partitioning 3.4.4 Device Memory Maps TABLE 3-3: PIC16(L)F1703/7 Memory Map (Banks 0-7) TABLE 3-4: PIC16(L)F1703/7 Memory Map (Banks 8-15) TABLE 3-5: PIC16(L)F1703/7 Memory Map (Banks 16-23) TABLE 3-6: PIC16(L)F1703/7 Memory Map (Banks 24-31) TABLE 3-7: PIC16(L)F1703/7 Memory Map (Banks 28-31) TABLE 3-8: PIC16(L)F1703/7 Memory Map, Bank 31 3.4.5 Core Function Registers Summary TABLE 3-9: Core Function Registers Summary TABLE 3-10: Special Function Register Summary 3.5 PCL and PCLATH FIGURE 3-3: Loading of PC in Different Situations 3.5.1 Modifying PCL 3.5.2 Computed GOTO 3.5.3 Computed Function Calls 3.5.4 Branching 3.6 Stack 3.6.1 Accessing the Stack FIGURE 3-4: Accessing the Stack Example 1 FIGURE 3-5: Accessing the Stack Example 2 FIGURE 3-6: Accessing the Stack Example 3 FIGURE 3-7: Accessing the Stack Example 4 3.6.2 Overflow/Underflow Reset 3.7 Indirect Addressing FIGURE 3-8: Indirect Addressing 3.7.1 Traditional Data Memory FIGURE 3-9: Traditional Data Memory Map 3.7.2 Linear Data Memory FIGURE 3-10: Linear Data Memory Map 3.7.3 Program Flash Memory FIGURE 3-11: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words 4.2 Register Definitions: Configuration Words Register 4-1: CONFIG1: Configuration Word 1 Register 4-2: CONFIG2: Configuration Word 2 4.3 Code Protection 4.3.1 Program Memory Protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device and Revision Register 4-3: DevID: Device ID Register Register 4-4: RevID: Revision ID Register 5.0 Resets FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit 5.1 Power-On Reset (POR) 5.1.1 Power-up Timer (PWRT) 5.2 Brown-Out Reset (BOR) TABLE 5-1: BOR Operating Modes 5.2.1 BOR is Always On 5.2.2 BOR is Off in Sleep 5.2.3 BOR Controlled by Software FIGURE 5-2: Brown-Out Situations 5.3 Register Definitions: BOR Control Register 5-1: BORCON: Brown-Out Reset Control Register 5.4 Low-Power Brown-Out Reset (LPBOR) 5.4.1 Enabling LPBOR 5.5 MCLR TABLE 5-2: MCLR Configuration 5.5.1 MCLR Enabled 5.5.2 MCLR Disabled 5.6 Watchdog Timer (WDT) Reset 5.7 RESET Instruction 5.8 Stack Overflow/Underflow Reset 5.9 Programming Mode Exit 5.10 Power-Up Timer 5.11 Start-up Sequence FIGURE 5-3: Reset Start-up Sequence 5.12 Determining the Cause of a Reset TABLE 5-3: Reset Status Bits and Their Significance TABLE 5-4: Reset Condition for Special Registers 5.13 Power Control (PCON) Register 5.14 Register Definitions: Power Control Register 5-2: PCON: Power Control Register TABLE 5-5: Summary of Registers Associated with Resets 6.0 Oscillator Module (with Fail-Safe Clock Monitor) 6.1 Overview FIGURE 6-1: Simplified PIC® MCU Clock Source Block Diagram 6.2 Clock Source Types 6.2.1 External Clock Sources FIGURE 6-2: External Clock (EC) Mode Operation 6.2.2 Internal Clock Sources FIGURE 6-3: Internal Oscillator Switch Timing 6.3 Clock Switching 6.3.1 System Clock Select (SCS) Bits TABLE 6-1: Oscillator Switching Delays 6.4 Register Definitions: Oscillator Control Register 6-1: OSCCON: Oscillator Control Register Register 6-2: OSCSTAT: Oscillator Status Register Register 6-3: OSCTUNE: Oscillator Tuning Register TABLE 6-2: Summary of Registers Associated with Clock Sources TABLE 6-3: Summary of Configuration Bits Associated with Clock Sources 7.0 Interrupts FIGURE 7-1: Interrupt Logic 7.1 Operation 7.2 Interrupt Latency FIGURE 7-2: Interrupt Latency FIGURE 7-3: INT Pin Interrupt Timing 7.3 Interrupts During Sleep 7.4 INT Pin 7.5 Automatic Context Saving 7.6 Register Definitions: Interrupt Control Register 7-1: INTCON: Interrupt Control Register Register 7-2: PIE1: Peripheral Interrupt Enable Register 1 Register 7-3: PIE2: Peripheral Interrupt Enable Register 2 Register 7-4: PIE3: Peripheral Interrupt Enable Register 3 Register 7-5: PIR1: Peripheral Interrupt Request Register 1 Register 7-6: PIR2: Peripheral Interrupt Request Register 2 Register 7-7: PIR3: Peripheral Interrupt Request Register 3 TABLE 7-1: Summary of Registers Associated with Interrupts 8.0 Power-Down Mode (Sleep) 8.1 Wake-up from Sleep 8.1.1 Wake-up Using Interrupts FIGURE 8-1: Wake-Up From Sleep Through Interrupt 8.2 Low-Power Sleep Mode 8.2.1 Sleep Current vs. Wake-up Time 8.2.2 Peripheral Usage in Sleep 8.3 Register Definitions: Voltage Regulator Control Register 8-1: VREGCON: Voltage Regulator Control Register(1) TABLE 8-1: Summary of Registers Associated with Power-Down Mode 9.0 Watchdog Timer (WDT) FIGURE 9-1: Watchdog Timer Block Diagram 9.1 Independent Clock Source 9.2 WDT Operating Modes 9.2.1 WDT is Always On 9.2.2 WDT is Off in Sleep 9.2.3 WDT Controlled By Software TABLE 9-1: WDT Operating Modes 9.3 Time-Out Period 9.4 Clearing the WDT 9.5 Operation During Sleep TABLE 9-2: WDT Clearing Conditions 9.6 Register Definitions: Watchdog Control Register 9-1: WDTCON: Watchdog Timer Control Register TABLE 9-3: Summary of Registers Associated with Watchdog Timer TABLE 9-4: Summary of Configuration Bits Associated with Watchdog Timer 10.0 Flash Program Memory Control 10.1 PMADRL and PMADRH Registers 10.1.1 PMCON1 and PMCON2 Registers 10.2 Flash Program Memory Overview TABLE 10-1: Flash Memory Organization By Device 10.2.1 Reading the Flash Program Memory FIGURE 10-1: Flash Program Memory Read Flowchart FIGURE 10-2: Flash Program Memory Read Cycle Execution EXAMPLE 10-1: Flash Program Memory Read 10.2.2 Flash Memory Unlock Sequence FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart 10.2.3 Erasing Flash Program Memory FIGURE 10-4: Flash Program Memory Erase Flowchart EXAMPLE 10-2: Erasing One Row of Program Memory 10.2.4 Writing to Flash Program Memory FIGURE 10-5: Block Writes to Flash Program Memory With 16 write latches FIGURE 10-6: Flash Program Memory Write Flowchart EXAMPLE 10-3: Writing to Flash Program Memory 10.3 Modifying Flash Program Memory FIGURE 10-7: Flash Program Memory Modify Flowchart 10.4 User ID, Device ID and Configuration Word Access TABLE 10-2: User ID, Device ID and Configuration Word Access (CFGS = 1) EXAMPLE 10-4: Configuration Word and Device ID Access 10.5 Write Verify FIGURE 10-8: Flash Program Memory Verify Flowchart 10.6 Register Definitions: Flash Program Memory Control Register 10-1: PMDATL: Program Memory Data Low Byte Register Register 10-2: PMDATH: Program Memory Data High Byte Register Register 10-3: PMADRL: Program Memory Address Low Byte Register Register 10-4: PMADRH: Program Memory Address High Byte Register Register 10-5: PMCON1: Program Memory Control 1 Register Register 10-6: PMCON2: Program Memory Control 2 Register TABLE 10-3: Summary of Registers Associated with Flash Program Memory TABLE 10-4: Summary of Configuration Bits Associated with Flash Program Memory 11.0 I/O Ports TABLE 11-1: Port Availability Per Device FIGURE 11-1: Generic I/O Port Operation 11.1 PORTA Registers 11.1.1 Data Register 11.1.2 Direction Control 11.1.3 Open Drain Control 11.1.4 Slew Rate Control 11.1.5 Input Threshold Control 11.1.6 Analog Control EXAMPLE 11-1: Initializing PORTA 11.1.7 PORTA Functions and Output Priorities 11.2 Register Definitions: PORTA Register 11-1: PORTA: PORTA Register Register 11-2: TRISA: PORTA Tri-State Register Register 11-3: LATA: PORTA Data Latch Register Register 11-4: ANSELA: PORTA Analog Select Register Register 11-5: WPUA: Weak Pull-Up PORTA Register Register 11-6: ODCONA: PORTA Open Drain Control Register Register 11-7: SLRCONA: PORTA Slew Rate Control Register Register 11-8: INLVLA: PORTA Input Level Control Register TABLE 11-2: Summary of Registers Associated with PORTA TABLE 11-3: Summary of Configuration Bits Associated with PORTA 11.3 PORTB Registers (PIC16(L)F1707 only) 11.3.1 Direction Control 11.3.2 Open Drain Control 11.3.3 Slew Rate Control 11.3.4 Input Threshold Control 11.3.5 Analog Control 11.3.6 PORTB Functions and Output Priorities 11.4 Register Definitions: PORTB Register 11-9: PORTB: PORTB Register Register 11-10: TRISB: PORTB Tri-State Register Register 11-11: LATB: PORTB Data Latch Register Register 11-12: ANSELB: PORTB Analog Select Register Register 11-13: WPUB: Weak Pull-Up PORTB Register Register 11-14: ODCONB: PORTB Open Drain Control Register Register 11-15: SLRCONB: PORTB Slew Rate Control Register Register 11-16: INLVLB: PORTB Input Level Control Register TABLE 11-4: Summary of Registers Associated with PORTB 11.5 PORTC Registers 11.5.1 Data Register 11.5.2 Direction Control 11.5.3 Input Threshold Control 11.5.4 Open Drain Control 11.5.5 Slew Rate Control 11.5.6 Analog Control 11.5.7 PORTC Functions and Output Priorities 11.6 Register Definitions: PORTC Register 11-17: PORTC: PORTC Register Register 11-18: TRISC: PORTC Tri-State Register Register 11-19: LATC: PORTC Data Latch Register Register 11-20: ANSELC: PORTC Analog Select Register Register 11-21: WPUC: Weak Pull-Up PORTC Register Register 11-22: ODCONC: PORTC Open Drain Control Register Register 11-23: SLRCONC: PORTC Slew Rate Control Register Register 11-24: INLVLC: PORTC Input Level Control Register TABLE 11-5: Summary of Registers Associated with PORTC 12.0 Peripheral Pin Select (PPS) Module 12.1 PPS Inputs 12.2 PPS Outputs FIGURE 12-1: Simplified PPS Block Diagram 12.3 Bidirectional Pins 12.4 PPS Lock EXAMPLE 12-1: PPS Lock/Unlock sequence 12.5 PPS Permanent Lock 12.6 Operation During Sleep 12.7 Effects of a Reset 12.8 Register Definitions: PPS Input Selection Register 12-1: xxxPPS: Peripheral xxx input Selection (PIC16(L)F1703) Register 12-2: xxxPPS: Peripheral xxx input Selection (PIC16(L)F1707) Register 12-3: RxyPPS: Pin Rxy Output Source Selection Register Register 12-4: PPSLOCK: PPS Lock Register TABLE 12-1: Summary of Registers Associated with the PPS Module 13.0 Interrupt-On-Change 13.1 Enabling the Module 13.2 Individual Pin Configuration 13.3 Interrupt Flags 13.4 Clearing Interrupt Flags EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example) 13.5 Operation in Sleep FIGURE 13-1: Interrupt-On-Change Block Diagram (PORTA Example) 13.6 Register Definitions: Interrupt-on-Change Control Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 13-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register(1) Register 13-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register(1) Register 13-6: IOCBF: Interrupt-on-Change PORTB Flag Register(1) Register 13-7: IOCCP: Interrupt-on-Change PORTC Positive Edge Register Register 13-8: IOCCN: Interrupt-on-Change PORTC Negative Edge Register Register 13-9: IOCCF: Interrupt-on-Change PORTC Flag Register TABLE 13-1: Summary of Registers Associated with Interrupt-On-Change 14.0 Fixed Voltage Reference (FVR) 14.1 Independent Gain Amplifiers 14.2 FVR Stabilization Period FIGURE 14-1: Voltage Reference Block Diagram TABLE 14-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 14.3 Register Definitions: FVR Control Register 14-1: FVRCON: Fixed Voltage Reference Control Register TABLE 14-2: Summary of Registers Associated with Fixed Voltage Reference 15.0 Temperature Indicator Module 15.1 Circuit Operation EQUATION 15-1: Vout Ranges FIGURE 15-1: Temperature Circuit Diagram 15.2 Minimum Operating Vdd TABLE 15-1: Recommended Vdd vs. Range 15.3 Temperature Output 15.4 ADC Acquisition Time TABLE 15-2: Summary of Registers Associated with the Temperature Indicator 16.0 Analog-to-Digital Converter (ADC) Module FIGURE 16-1: ADC Block Diagram 16.1 ADC Configuration 16.1.1 Port Configuration 16.1.2 Channel Selection 16.1.3 ADC Voltage Reference 16.1.4 Conversion Clock TABLE 16-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 16-2: Analog-to-Digital Conversion Tad Cycles 16.1.5 Interrupts 16.1.6 Result Formatting FIGURE 16-3: 10-Bit ADC Conversion Result Format 16.2 ADC Operation 16.2.1 Starting a Conversion 16.2.2 Completion of a Conversion 16.2.3 Terminating a Conversion 16.2.4 ADC Operation During Sleep 16.2.5 Auto-Conversion Trigger TABLE 16-2: Auto-Conversion Sources 16.2.6 ADC Conversion Procedure EXAMPLE 16-1: ADC Conversion 16.3 Register Definitions: ADC Control Register 16-1: ADCON0: ADC Control Register 0 Register 16-2: ADCON1: ADC Control Register 1 Register 16-3: ADCON2: ADC Control Register 2 Register 16-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 16-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 16-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 16-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 16.4 ADC Acquisition Requirements EQUATION 16-1: Acquisition Time Example FIGURE 16-4: Analog Input Model FIGURE 16-5: ADC Transfer Function TABLE 16-3: Summary of Registers Associated with ADC 17.0 Operational Amplifier (OPA) Modules FIGURE 17-1: OPAx Module Block Diagram 17.1 OPA Module Performance 17.1.1 OPA Module Control 17.1.2 Unity Gain Mode 17.2 Effects of Reset 17.3 Register Definitions: Op Amp Control Register 17-1: OPAxCON: Operational Amplifiers (OPAx) Control Registers TABLE 17-1: Summary of Registers Associated with Op Amps 18.0 Zero-Cross Detection (ZCD) Module 18.1 External Resistor Selection EQUATION 18-1: External Resistor FIGURE 18-1: External Voltage FIGURE 18-2: Simplified ZCD Block Diagram 18.2 ZCD Logic Output 18.3 ZCD Logic Polarity 18.4 ZCD Interrupts 18.5 Correcting for Vref offset EQUATION 18-2: ZCD Event Offset EQUATION 18-3: ZCD Pull-up/down EQUATION 18-4: 18.6 Handling Vpeak variations EQUATION 18-5: Series R for V range 18.7 Operation During Sleep 18.8 Effects of a Reset 18.9 Register Definitions: ZCD Control Register 18-1: ZCDxCON: Zero Cross Detection Control Register TABLE 18-1: Summary of Registers Associated with the ZCD Module TABLE 18-2: Summary of Configuration Bits Associated with the ZCD Module 19.0 Timer0 Module 19.1 Timer0 Operation 19.1.1 8-bit Timer Mode 19.1.2 8-bit Counter Mode FIGURE 19-1: Block Diagram of the Timer0 19.1.3 Software Programmable Prescaler 19.1.4 Timer0 Interrupt 19.1.5 8-bit Counter Mode Synchronization 19.1.6 Operation During Sleep 19.2 Register Definitions: Option Register Register 19-1: OPTION_REG: OPTION Register TABLE 19-1: Summary of Registers Associated with Timer0 20.0 Timer1 Module with Gate Control FIGURE 20-1: Timer1 Block Diagram 20.1 Timer1 Operation TABLE 20-1: Timer1 Enable Selections 20.2 Clock Source Selection 20.2.1 Internal Clock Source 20.2.2 External Clock Source TABLE 20-2: Clock Source Selections 20.3 Timer1 Prescaler 20.4 Timer1 Operation in Asynchronous Counter Mode 20.4.1 Reading and Writing Timer1 in Asynchronous Counter Mode 20.5 Timer1 Gate 20.5.1 Timer1 Gate Enable TABLE 20-3: Timer1 Gate Enable Selections 20.5.2 Timer1 Gate Source Selection TABLE 20-4: Timer1 Gate Sources 20.5.3 Timer1 Gate Toggle Mode 20.5.4 Timer1 Gate Single-Pulse Mode 20.5.5 Timer1 Gate Value Status 20.5.6 Timer1 Gate Event Interrupt 20.6 Timer1 Interrupt 20.7 Timer1 Operation During Sleep 20.8 CCP Capture/Compare Time Base 20.9 CCP Auto-Conversion Trigger FIGURE 20-2: Timer1 Incrementing Edge FIGURE 20-3: Timer1 Gate Enable Mode FIGURE 20-4: Timer1 Gate Toggle Mode FIGURE 20-5: Timer1 Gate Single-Pulse Mode FIGURE 20-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 20.10 Register Definitions: Timer1 Control Register 20-1: T1CON: Timer1 Control Register Register 20-2: T1GCON: Timer1 Gate Control Register TABLE 20-5: Summary of Registers Associated with Timer1 21.0 Timer2 Module FIGURE 21-1: Timer2 Block Diagram 21.1 Timer2 Operation 21.2 Timer2 Interrupt 21.3 Timer2 Output 21.4 Timer2 Operation During Sleep 21.5 Register Definitions: Timer2 Control Register 21-1: T2CON: Timer2 Control Register TABLE 21-1: Summary of Registers Associated with Timer2 22.0 Capture/Compare/PWM Modules 22.1 Capture Mode 22.1.1 CCP Pin Configuration FIGURE 22-1: Capture Mode Operation Block Diagram 22.1.2 Timer1 Mode Resource 22.1.3 Software Interrupt Mode 22.1.4 CCP Prescaler EXAMPLE 22-1: Changing Between Capture Prescalers 22.1.5 Capture During Sleep 22.2 Compare Mode FIGURE 22-2: Compare Mode Operation Block Diagram 22.2.1 CCPx Pin Configuration 22.2.2 Timer1 Mode Resource 22.2.3 Software Interrupt Mode 22.2.4 Auto-Conversion Trigger 22.2.5 Compare During Sleep 22.3 PWM Overview 22.3.1 Standard PWM Operation FIGURE 22-3: CCP PWM Output Signal FIGURE 22-4: Simplified PWM Block Diagram 22.3.2 Setup for PWM Operation 22.3.3 Timer2 Timer Resource 22.3.4 PWM Period EQUATION 22-1: PWM Period 22.3.5 PWM Duty Cycle EQUATION 22-2: Pulse Width EQUATION 22-3: Duty Cycle Ratio 22.3.6 PWM Resolution EQUATION 22-4: PWM Resolution TABLE 22-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 22-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 22.3.7 Operation in Sleep Mode 22.3.8 Changes in System Clock Frequency 22.3.9 Effects of Reset TABLE 22-3: Summary of Registers Associated with Standard PWM 22.4 Register Definitions: CCP Control Register 22-1: CCPXCON: CCPx Control Register 23.0 Master Synchronous Serial Port (MSSP) Module 23.1 MSSP Module Overview FIGURE 23-1: MSSP Block Diagram (SPI mode) FIGURE 23-2: MSSP Block Diagram (I2C Master mode) FIGURE 23-3: MSSP Block Diagram (I2C Slave mode) 23.2 SPI Mode Overview FIGURE 23-4: SPI Master and Multiple Slave Connection 23.2.1 SPI Mode Registers 23.2.2 SPI Mode Operation FIGURE 23-5: SPI Master/Slave Connection 23.2.3 SPI Master Mode FIGURE 23-6: SPI Mode Waveform (Master Mode) 23.2.4 SPI Slave Mode 23.2.5 Slave Select Synchronization FIGURE 23-7: SPI Daisy-Chain Connection FIGURE 23-8: Slave Select Synchronous Waveform FIGURE 23-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 23-10: SPI Mode Waveform (Slave Mode with CKE = 1) 23.2.6 SPI Operation in Sleep Mode TABLE 23-1: Summary of Registers Associated with SPI Operation 23.3 I2C Mode Overview FIGURE 23-11: I2C Master/ Slave Connection 23.3.1 Clock Stretching 23.3.2 Arbitration 23.4 I2C Mode Operation 23.4.1 Byte Format 23.4.2 Definition of I2C Terminology 23.4.3 SDA and SCL Pins 23.4.4 SDA Hold Time TABLE 23-2: I2C Bus terms 23.4.5 Start Condition 23.4.6 Stop Condition 23.4.7 Restart Condition 23.4.8 Start/Stop Condition Interrupt masking FIGURE 23-12: I2C Start and Stop Conditions FIGURE 23-13: I2C Restart Condition 23.4.9 Acknowledge Sequence 23.5 I2C Slave Mode Operation 23.5.1 Slave Mode Addresses 23.5.2 Slave Reception FIGURE 23-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 23-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 23-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 23-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) 23.5.3 Slave Transmission FIGURE 23-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) FIGURE 23-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) 23.5.4 Slave Mode 10-bit Address Reception 23.5.5 10-bit Addressing with Address or Data Hold FIGURE 23-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 23-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 23-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) 23.5.6 Clock Stretching 23.5.7 Clock Synchronization and the CKP bit FIGURE 23-23: Clock Synchronization Timing 23.5.8 General Call Address Support FIGURE 23-24: Slave Mode General Call Address Sequence 23.5.9 SSP Mask Register 23.6 I2C Master Mode 23.6.1 I2C Master Mode Operation 23.6.2 Clock Arbitration FIGURE 23-25: Baud Rate Generator Timing with Clock Arbitration 23.6.3 WCOL Status Flag 23.6.4 I2C Master Mode Start Condition Timing FIGURE 23-26: First Start Bit Timing 23.6.5 I2C Master Mode Repeated Start Condition Timing FIGURE 23-27: Repeated Start Condition Waveform 23.6.6 I2C Master Mode Transmission FIGURE 23-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) 23.6.7 I2C Master Mode Reception FIGURE 23-29: I2C Master Mode Waveform (Reception, 7-bit Address) 23.6.8 Acknowledge Sequence Timing 23.6.9 Stop Condition Timing FIGURE 23-30: Acknowledge Sequence Waveform FIGURE 23-31: Stop Condition Receive or Transmit Mode 23.6.10 Sleep Operation 23.6.11 Effects of a Reset 23.6.12 Multi-Master Mode 23.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration FIGURE 23-32: Bus Collision Timing for Transmit and Acknowledge FIGURE 23-33: Bus Collision During Start Condition (SDA Only) FIGURE 23-34: Bus Collision During Start Condition (SCL = 0) FIGURE 23-35: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 23-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 23-37: Bus Collision During Repeated Start Condition (Case 2) FIGURE 23-38: Bus Collision During a Stop Condition (Case 1) FIGURE 23-39: Bus Collision During a Stop Condition (Case 2) TABLE 23-3: Summary of Registers Associated with I2C Operation 23.7 Baud Rate Generator FIGURE 23-40: Baud Rate Generator Block Diagram TABLE 23-4: MSSP Clock Rate w/BRG 23.8 Register Definitions: MSSP Control Register 23-1: SSP1STAT: SSP STATUS Register Register 23-2: SSP1CON1: SSP Control Register 1 Register 23-3: SSP1CON2: SSP Control Register 2(1) Register 23-4: SSP1CON3: SSP Control Register 3 Register 23-5: SSP1MSK: SSP Mask Register Register 23-6: SSPxADD: MSSP Address and Baud Rate Register (I2C Mode) 24.0 In-Circuit Serial Programming™ (ICSP™) 24.1 High-Voltage Programming Entry Mode 24.2 Low-Voltage Programming Entry Mode 24.3 Common Programming Interfaces FIGURE 24-1: ICD RJ-11 Style Connector Interface FIGURE 24-2: PICkit™ Programmer Style Connector Interface FIGURE 24-3: Typical Connection for ICSP™ Programming 25.0 Instruction Set Summary 25.1 Read-Modify-Write Operations TABLE 25-1: Opcode Field Descriptions TABLE 25-2: Abbreviation Descriptions FIGURE 25-1: General Format for Instructions TABLE 25-3: PIC16(L)F1703/7 Instruction Set TABLE 25-3: PIC16(L)F1703/7 Instruction Set (Continued) 25.2 Instruction Descriptions 26.0 Electrical Specifications 26.1 Absolute Maximum Ratings(†) 26.2 Standard Operating Conditions FIGURE 26-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F1703/7 Only FIGURE 26-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF1703/7 Only 26.3 DC Characteristics TABLE 26-1: Supply Voltage FIGURE 26-3: POR and POR Rearm with Slow Rising Vdd TABLE 26-2: Supply Current (Idd)(1,2) TABLE 26-3: Power-Down Currents (Ipd)(1,2) TABLE 26-4: I/O Ports TABLE 26-5: Memory Programming Specifications TABLE 26-6: Thermal Characteristics 26.4 AC Characteristics FIGURE 26-4: Load Conditions FIGURE 26-5: Clock Timing TABLE 26-7: Clock Oscillator Timing Requirements TABLE 26-8: Oscillator Parameters FIGURE 26-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 26-9: PLL Clock Timing Specifications FIGURE 26-7: CLKOUT and I/O Timing TABLE 26-10: CLKOUT and I/O Timing Parameters FIGURE 26-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 26-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters FIGURE 26-9: Timer0 and Timer1 External Clock Timings FIGURE 26-10: Brown-Out Reset Timing and Characteristics TABLE 26-12: Timer0 and Timer1 External Clock Requirements FIGURE 26-11: Capture/Compare/PWM Timings (CCP) TABLE 26-13: Capture/Compare/PWM Requirements (CCP) TABLE 26-14: Analog-to-Digital Converter (ADC) Characteristics(1,2,3) TABLE 26-15: ADC Conversion Requirements FIGURE 26-12: ADC Conversion Timing (ADC Clock Fosc-based) FIGURE 26-13: ADC Conversion Timing (ADC Clock from FRC) TABLE 26-16: Operational Amplifier (OPA) TABLE 26-17: Zero Cross Pin Specifications FIGURE 26-14: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 26-15: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 26-16: SPI Slave Mode Timing (CKE = 0) FIGURE 26-17: SPI Slave Mode Timing (CKE = 1) TABLE 26-18: SPI Mode requirements FIGURE 26-18: I2C Bus Start/Stop Bits Timing TABLE 26-19: I2C Bus Start/Stop Bits Requirements FIGURE 26-19: I2C Bus Data Timing TABLE 26-20: I2C Bus Data Requirements 27.0 DC and AC Characteristics Graphs and Charts 28.0 Development Support 28.1 MPLAB X Integrated Development Environment Software 28.2 MPLAB XC Compilers 28.3 MPASM Assembler 28.4 MPLINK Object Linker/ MPLIB Object Librarian 28.5 MPLAB Assembler, Linker and Librarian for Various Device Families 28.6 MPLAB X SIM Software Simulator 28.7 MPLAB REAL ICE In-Circuit Emulator System 28.8 MPLAB ICD 3 In-Circuit Debugger System 28.9 PICkit 3 In-Circuit Debugger/ Programmer 28.10 MPLAB PM3 Device Programmer 28.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 28.12 Third-Party Development Tools 29.0 Packaging Information 29.1 Package Marking Information Package Marking Information (Continued) Package Marking Information (Continued) 29.2 Package Details Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales