Datasheet ATmega16U4, ATmega32U4 - Complete (Microchip) - 7

link to page 53
2.2.14 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-2 on page 53. Shorter pulses are not guaranteed to generate a reset.
2.2.15 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.16 XTAL2
Output from the inverting Oscillator amplifier.
2.2.17 AVCC
AVCC is the supply voltage pin (input) for all the A/D Converter channels. If the ADC is not used, it should be externally connected to VCC. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.2.18 AREF
This is the analog reference pin (input) for the A/D Converter. ATmega16U4/32U4 [DATASHEET ] 7 Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 Document Outline Features 1. Pin Configurations 2. Overview 2.1 Block Diagram 2.2 Pin Descriptions 2.2.1 VCC 2.2.2 GND 2.2.3 Port B (PB7..PB0) 2.2.4 Port C (PC7,PC6) 2.2.5 Port D (PD7..PD0) 2.2.6 Port E (PE6,PE2) 2.2.7 Port F (PF7..PF4, PF1,PF0) 2.2.8 D- 2.2.9 D+ 2.2.10 UGND 2.2.11 UVCC 2.2.12 UCAP 2.2.13 VBUS 2.2.14 RESET 2.2.15 XTAL1 2.2.16 XTAL2 2.2.17 AVCC 2.2.18 AREF 3. About 3.1 Disclaimer 3.2 Resources 3.3 Code Examples 3.4 Data Retention 4. AVR CPU Core 4.1 Introduction 4.2 Architectural Overview 4.3 ALU – Arithmetic Logic Unit 4.4 Status Register 4.5 General Purpose Register File 4.5.1 The X-register, Y-register, and Z-register 4.6 Stack Pointer 4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ 4.7 Instruction Execution Timing 4.8 Reset and Interrupt Handling 4.8.1 Interrupt Response Time 5. AVR Memories 5.1 In-System Reprogrammable Flash Program Memory 5.2 SRAM Data Memory 5.2.1 Data Memory Access Times 5.3 EEPROM Data Memory 5.3.1 EEPROM Read/Write Access 5.3.2 The EEPROM Address Register – EEARH and EEARL 5.3.3 The EEPROM Data Register – EEDR 5.3.4 The EEPROM Control Register – EECR 5.3.5 Preventing EEPROM Corruption 5.4 I/O Memory 5.4.1 General Purpose I/O Registers 5.4.2 General Purpose I/O Register 2 – GPIOR2 5.4.3 General Purpose I/O Register 1 – GPIOR1 5.4.4 General Purpose I/O Register 0 – GPIOR0 6. System Clock and Clock Options 6.1 Clock Systems and their Distribution 6.1.1 CPU Clock – clkCPU 6.1.2 I/O Clock – clkI/O 6.1.3 Flash Clock – clkFLASH 6.1.4 ADC Clock – clkADC 6.1.5 PLL Prescaler Clock – clkPllPresc 6.1.6 PLL Output Clock – clkPll 6.1.7 High-Speed Timer Clock– clkTMR 6.1.8 USB Clock – clkUSB 6.2 Clock Sources 6.2.1 Default Clock Source ATmega16U4 and ATmega32U4 6.2.2 Default Clock Source ATmega16U4RC and ATmega32U4RC 6.2.3 Clock Startup Sequence 6.3 Low Power Crystal Oscillator 6.4 Low Frequency Crystal Oscillator 6.5 Calibrated Internal RC Oscillator 6.5.1 Oscillator Calibration Register – OSCCAL 6.5.2 Oscillator Control Register – RCCTRL 6.6 External Clock 6.7 Clock Switch 6.7.1 Example of use 6.8 Clock Output Buffer 6.8.1 System Clock Prescaler 6.9 PLL 6.9.1 Internal PLL 6.10 Clock switch Algorithm 6.10.1 Switch from External Clock to RC Clock 6.10.2 Switch from RC Clock to External Clock 6.11 Register Description 6.11.1 CLKSEL0 – Clock Selection Register 0 6.11.2 CLKSEL1 – Clock Selection Register 1 6.11.3 CLKSTA – Clock Status Register 6.11.4 CLKPR – Clock Prescaler Register 6.11.5 PLL Control and Status Register – PLLCSR 6.11.6 PLL Frequency Control Register – PLLFRQ 7. Power Management and Sleep Modes 7.1 Idle Mode 7.2 ADC Noise Reduction Mode 7.3 Power-down Mode 7.4 Power-save Mode 7.5 Standby Mode 7.6 Extended Standby Mode 7.7 Power Reduction Register 7.8 Minimizing Power Consumption 7.8.1 Analog to Digital Converter 7.8.2 Analog Comparator 7.8.3 Brown-out Detector 7.8.4 Internal Voltage Reference 7.8.5 Watchdog Timer 7.8.6 Port Pins 7.8.7 On-chip Debug System 7.9 Register Description 7.9.1 Sleep Mode Control Register – SMCR 7.9.2 Power Reduction Register 0 - PRR0 7.9.3 Power Reduction Register 1 - PRR1 8. System Control and Reset 8.1 Resetting the AVR 8.2 Reset Sources 8.3 Power-on Reset 8.4 External Reset 8.5 Brown-out Detection 8.6 Watchdog Reset 8.7 USB Reset 8.8 Internal Voltage Reference 8.8.1 Voltage Reference Enable Signals and Start-up Time 8.9 Watchdog Timer 8.10 Register Description 8.11 MCU Status Register – MCUSR 8.11.1 Watchdog Timer Control Register - WDTCSR 9. Interrupts 9.1 Interrupt Vectors in ATmega16U4/ATmega32U4 9.1.1 Moving Interrupts Between Application and Boot Space 9.2 Register Description 9.2.1 MCU Control Register – MCUCR 10. I/O-Ports 10.1 Introduction 10.2 Ports as General Digital I/O 10.2.1 Configuring the Pin 10.2.2 Toggling the Pin 10.2.3 Switching Between Input and Output 10.2.4 Reading the Pin Value 10.2.5 Digital Input Enable and Sleep Modes 10.2.6 Unconnected Pins 10.3 Alternate Port Functions 10.3.1 Alternate Functions of Port B 10.3.2 Alternate Functions of Port C 10.3.3 Alternate Functions of Port D 10.3.4 Alternate Functions of Port E 10.3.5 Alternate Functions of Port F 10.4 Register Description for I/O-Ports 10.4.1 MCU Control Register – MCUCR 10.4.2 Port B Data Register – PORTB 10.4.3 Port B Data Direction Register – DDRB 10.4.4 Port B Input Pins Address – PINB 10.4.5 Port C Data Register – PORTC 10.4.6 Port C Data Direction Register – DDRC 10.4.7 Port C Input Pins Address – PINC 10.4.8 Port D Data Register – PORTD 10.4.9 Port D Data Direction Register – DDRD 10.4.10 Port D Input Pins Address – PIND 10.4.11 Port E Data Register – PORTE 10.4.12 Port E Data Direction Register – DDRE 10.4.13 Port E Input Pins Address – PINE 10.4.14 Port F Data Register – PORTF 10.4.15 Port F Data Direction Register – DDRF 10.4.16 Port F Input Pins Address – PINF 11. External Interrupts 11.1 Register Description 11.1.1 External Interrupt Control Register A – EICRA 11.1.2 External Interrupt Control Register B – EICRB 11.1.3 External Interrupt Mask Register – EIMSK 11.1.4 External Interrupt Flag Register – EIFR 11.1.5 Pin Change Interrupt Control Register - PCICR 11.1.6 Pin Change Interrupt Flag Register – PCIFR 11.1.7 Pin Change Mask Register 0 – PCMSK0 12. Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers 12.1 Internal Clock Source 12.2 Prescaler Reset 12.3 External Clock Source 12.4 Register Description 12.4.1 General Timer/Counter Control Register – GTCCR 13. 8-bit Timer/Counter0 with PWM 13.1 Overview 13.1.1 Registers 13.1.2 Definitions 13.2 Timer/Counter Clock Sources 13.3 Counter Unit 13.4 Output Compare Unit 13.4.1 Force Output Compare 13.4.2 Compare Match Blocking by TCNT0 Write 13.4.3 Using the Output Compare Unit 13.5 Compare Match Output Unit 13.5.1 Compare Output Mode and Waveform Generation 13.6 Modes of Operation 13.6.1 Normal Mode 13.6.2 Clear Timer on Compare Match (CTC) Mode 13.6.3 Fast PWM Mode 13.6.4 Phase Correct PWM Mode 13.7 Timer/Counter Timing Diagrams 13.8 8-bit Timer/Counter Register Description 13.8.1 Timer/Counter Control Register A – TCCR0A 13.8.2 Timer/Counter Control Register B – TCCR0B 13.8.3 Timer/Counter Register – TCNT0 13.8.4 Output Compare Register A – OCR0A 13.8.5 Output Compare Register B – OCR0B 13.8.6 Timer/Counter Interrupt Mask Register – TIMSK0 13.8.7 Timer/Counter 0 Interrupt Flag Register – TIFR0 14. 16-bit Timers/Counters (Timer/Counter1 and Timer/Counter3) 14.1 Overview 14.1.1 Registers 14.1.2 Definitions 14.2 Accessing 16-bit Registers 14.2.1 Reusing the Temporary High Byte Register 14.3 Timer/Counter Clock Sources 14.4 Counter Unit 14.5 Input Capture Unit 14.5.1 Input Capture Trigger Source 14.5.2 Noise Canceler 14.5.3 Using the Input Capture Unit 14.6 Output Compare Units 14.6.1 Force Output Compare 14.6.2 Compare Match Blocking by TCNTn Write 14.6.3 Using the Output Compare Unit 14.7 Compare Match Output Unit 14.7.1 Compare Output Mode and Waveform Generation 14.8 Modes of Operation 14.8.1 Normal Mode 14.8.2 Clear Timer on Compare Match (CTC) Mode 14.8.3 Fast PWM Mode 14.8.4 Phase Correct PWM Mode 14.8.5 Phase and Frequency Correct PWM Mode 14.9 Timer/Counter Timing Diagrams 14.10 16-bit Timer/Counter Register Description 14.10.1 Timer/Counter1 Control Register A – TCCR1A 14.10.2 Timer/Counter3 Control Register A – TCCR3A 14.10.3 Timer/Counter1 Control Register B – TCCR1B 14.10.4 Timer/Counter3 Control Register B – TCCR3B 14.10.5 Timer/Counter1 Control Register C – TCCR1C 14.10.6 Timer/Counter3 Control Register C – TCCR3C 14.10.7 Timer/Counter1 – TCNT1H and TCNT1L 14.10.8 Timer/Counter3 – TCNT3H and TCNT3L 14.10.9 Output Compare Register 1 A – OCR1AH and OCR1AL 14.10.10 Output Compare Register 1 B – OCR1BH and OCR1BL 14.10.11 Output Compare Register 1 C – OCR1CH and OCR1CL 14.10.12 Output Compare Register 3 A – OCR3AH and OCR3AL 14.10.13 Output Compare Register 3 B – OCR3BH and OCR3BL 14.10.14 Output Compare Register 3 C – OCR3CH and OCR3CL 14.10.15 Input Capture Register 1 – ICR1H and ICR1L 14.10.16 Input Capture Register 3 – ICR3H and ICR3L 14.10.17 Timer/Counter1 Interrupt Mask Register – TIMSK1 14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3 14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1 14.10.20 Timer/Counter3 Interrupt Flag Register – TIFR3 15. 10-bit High Speed Timer/Counter4 15.1 Features 15.2 Overview 15.2.1 Speed 15.2.2 Accuracy 15.2.3 Registers 15.2.4 Synchronization 15.2.5 Definitions 15.3 Counter Unit 15.3.1 Counter Initialization for Asynchronous Mode 15.4 Output Compare Unit 15.4.1 Force Output Compare 15.4.2 Compare Match Blocking by TCNT4 Write 15.4.3 Using the Output Compare Unit 15.5 Dead Time Generator 15.6 Compare Match Output Unit 15.6.1 Compare Output Mode and Waveform Generation 15.6.2 Enhanced Compare/PWM mode 15.7 Synchronous update 15.8 Modes of Operation 15.8.1 Normal Mode 15.8.2 Fast PWM Mode 15.8.3 Phase and Frequency Correct PWM Mode 15.8.4 PWM6 Mode 15.9 Timer/Counter Timing Diagrams 15.10 Fault Protection Unit 15.10.1 Fault Protection Trigger Source 15.10.2 Noise Canceler 15.11 Accessing 10-bit Registers 15.11.1 Reusing the Temporary High Byte Register 15.12 Register Description 15.12.1 TCCR4A – Timer/Counter4 Control Register A 15.12.2 TCCR4B – Timer/Counter4 Control Register B 15.12.3 TCCR4C – Timer/Counter4 Control Register C 15.12.4 TCCR4D – Timer/Counter4 Control Register D 15.12.5 TCCR4E – Timer/Counter4 Control Register E 15.12.6 TCNT4 – Timer/Counter4 15.12.7 TC4H – Timer/Counter4 High Byte 15.12.8 OCR4A – Timer/Counter4 Output Compare Register A 15.12.9 OCR4B – Timer/Counter4 Output Compare Register B 15.12.10 OCR4C – Timer/Counter4 Output Compare Register C 15.12.11 OCR4D – Timer/Counter4 Output Compare Register D 15.12.12 TIMSK4 – Timer/Counter4 Interrupt Mask Register 15.12.13 TIFR4 – Timer/Counter4 Interrupt Flag Register 15.12.14 DT4 – Timer/Counter4 Dead Time Value 16. Output Compare Modulator (OCM1C0A) 16.1 Overview 16.2 Description 16.2.1 Timing Example 17. Serial Peripheral Interface – SPI 17.1 SS Pin Functionality 17.1.1 Slave Mode 17.1.2 Master Mode 17.1.3 Data Modes 17.2 Register Description 17.2.1 SPI Control Register – SPCR 17.2.2 SPI Status Register – SPSR 17.2.3 SPI Data Register – SPDR 18. USART 18.1 Overview 18.2 Clock Generation 18.2.1 Internal Clock Generation – The Baud Rate Generator 18.2.2 Double Speed Operation (U2Xn) 18.2.3 External Clock 18.2.4 Synchronous Clock Operation 18.3 Frame Formats 18.3.1 Parity Bit Calculation 18.4 USART Initialization 18.5 Data Transmission – The USART Transmitter 18.5.1 Sending Frames with 5 to 8 Data Bit 18.5.2 Sending Frames with 9 Data Bit 18.5.3 Transmitter Flags and Interrupts 18.5.4 Parity Generator 18.5.5 Disabling the Transmitter 18.6 Data Reception – The USART Receiver 18.6.1 Receiving Frames with 5 to 8 Data Bits 18.6.2 Receiving Frames with 9 Data Bits 18.6.3 Receive Compete Flag and Interrupt 18.6.4 Receiver Error Flags 18.6.5 Parity Checker 18.6.6 Disabling the Receiver 18.6.7 Flushing the Receive Buffer 18.7 Asynchronous Data Reception 18.7.1 Asynchronous Clock Recovery 18.7.2 Asynchronous Data Recovery 18.7.3 Asynchronous Operational Range 18.8 Multi-processor Communication Mode 18.8.1 Using MPCMn 18.9 Hardware Flow Control 18.9.1 Receiver Flow Control 18.9.2 Transmission Flow Control 18.10 Examples of Baud Rate Setting 18.11 USART Register Description 18.11.1 USART I/O Data Register n– UDRn 18.11.2 USART Control and Status Register A – UCSRnA 18.11.3 USART Control and Status Register n B – UCSRnB 18.11.4 USART Control and Status Register n C – UCSRnC 18.11.5 USART Control and Status Register n D– UCSRnD 18.11.6 USART Baud Rate Registers – UBRRLn and UBRRHn 19. USART in SPI Mode 19.1 Overview 19.2 Clock Generation 19.3 SPI Data Modes and Timing 19.4 Frame Formats 19.4.1 USART MSPIM Initialization 19.5 Data Transfer 19.5.1 Transmitter and Receiver Flags and Interrupts 19.5.2 Disabling the Transmitter or Receiver 19.6 AVR USART MSPIM vs. AVR SPI 19.7 USART MSPIM Register Description 19.7.1 USART MSPIM I/O Data Register - UDRn 19.7.2 USART MSPIM Control and Status Register n A - UCSRnA 19.7.3 USART MSPIM Control and Status Register n B - UCSRnB 19.7.4 USART MSPIM Control and Status Register n C - UCSRnC 19.7.5 USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH 20. 2-wire Serial Interface 20.1 Features 20.2 2-wire Serial Interface Bus Definition 20.2.1 TWI Terminology 20.2.2 Electrical Interconnection 20.3 Data Transfer and Frame Format 20.3.1 Transferring Bits 20.3.2 START and STOP Conditions 20.3.3 Address Packet Format 20.3.4 Data Packet Format 20.3.5 Combining Address and Data Packets into a Transmission 20.4 Multi-master Bus Systems, Arbitration and Synchronization 20.5 Overview of the TWI Module 20.5.1 SCL and SDA Pins 20.5.2 Bit Rate Generator Unit 20.5.3 Bus Interface Unit 20.5.4 Address Match Unit 20.5.5 Control Unit 20.6 Using the TWI 20.7 Transmission Modes 20.7.1 Master Transmitter Mode 20.7.2 Master Receiver Mode 20.7.3 Slave Receiver Mode 20.7.4 Slave Transmitter Mode 20.7.5 Miscellaneous States 20.7.6 Combining Several TWI Modes 20.8 Multi-master Systems and Arbitration 20.9 TWI Register Description 20.9.1 TWI Bit Rate Register – TWBR 20.9.2 TWI Control Register – TWCR 20.9.3 TWI Status Register – TWSR 20.9.4 TWI Data Register – TWDR 20.9.5 TWI (Slave) Address Register – TWAR 20.9.6 TWI (Slave) Address Mask Register – TWAMR 21. USB Controller 21.1 Features 21.2 Block Diagram 21.3 Typical Application Implementation 21.3.1 Bus Powered Device 21.3.2 Self Powered Device 21.4 Crystal-less Operation 21.5 Design Guidelines 21.6 General Operating Modes 21.6.1 Introduction 21.6.2 Power-on and Reset 21.6.3 Interrupts 21.7 Power Modes 21.7.1 Idle Mode 21.7.2 Power Down 21.7.3 Freeze Clock 21.8 Speed Control 21.9 Memory Management 21.10 PAD Suspend 21.11 Plug-in Detection 21.12 USB Software Operating Modes 21.13 Registers Description 21.13.1 USB General Registers 22. USB Device Operating Modes 22.1 Introduction 22.2 Power-on and Reset 22.3 Endpoint Reset 22.4 USB Reset 22.5 Endpoint Selection 22.6 Endpoint Activation 22.7 Address Setup 22.8 Suspend, Wake-up and Resume 22.9 Detach 22.10 Remote Wake-up 22.11 STALL Request 22.11.1 Special Consideration for Control Endpoints 22.11.2 STALL Handshake and Retry Mechanism 22.12 CONTROL Endpoint Management 22.12.1 Control Write 22.12.2 Control Read 22.13 OUT Endpoint Management 22.13.1 Overview 22.13.2 Detailed description 22.13.2.1 22.14 IN endpoint management 22.14.1 Detailed Description 22.14.1.1 Abort 22.15 Isochronous Mode 22.15.1 Underflow 22.15.2 CRC Error 22.16 Overflow 22.17 Interrupts 22.18 Registers 22.18.1 USB Device General Registers 22.18.2 USB Device Endpoint Registers 23. Analog Comparator 23.1 Register Description 23.1.1 ADC Control and Status Register B – ADCSRB 23.1.2 Analog Comparator Control and Status Register – ACSR 23.2 Analog Comparator Multiplexed Input 23.2.1 Digital Input Disable Register 1 – DIDR1 24. Analog to Digital Converter - ADC 24.1 Features 24.2 Operation 24.3 Starting a Conversion 24.4 Prescaling and Conversion Timing 24.4.1 Differential Channels 24.5 Changing Channel or Reference Selection 24.5.1 ADC Input Channels 24.5.2 ADC Voltage Reference 24.6 Temperature Sensor 24.6.1 Sensor Calibration 24.7 ADC Noise Canceler 24.7.1 Analog Input Circuitry 24.7.2 Analog Noise Canceling Techniques 24.7.3 Offset Compensation Schemes 24.7.4 ADC Accuracy Definitions 24.8 ADC Conversion Result 24.9 ADC Register Description 24.9.1 ADC Multiplexer Selection Register – ADMUX 24.9.2 ADC Control and Status Register A – ADCSRA 24.9.3 The ADC Data Register – ADCL and ADCH 24.9.3.1 ADLAR = 0 24.9.3.2 ADLAR = 1 24.9.4 ADC Control and Status Register B – ADCSRB 24.9.5 Digital Input Disable Register 0 – DIDR0 24.9.6 Digital Input Disable Register 2 – DIDR2 25. JTAG Interface and On-chip Debug System 25.0.1 Features 25.1 Overview 25.2 Test Access Port – TAP 25.3 TAP Controller 25.4 Using the Boundary-scan Chain 25.5 Using the On-chip Debug System 25.6 On-chip Debug Specific JTAG Instructions 25.6.1 PRIVATE0; 0x8 25.6.2 PRIVATE1; 0x9 25.6.3 PRIVATE2; 0xA 25.6.4 PRIVATE3; 0xB 25.7 On-chip Debug Related Register in I/O Memory 25.7.1 On-chip Debug Register – OCDR 25.8 Using the JTAG Programming Capabilities 25.9 Bibliography 26. IEEE 1149.1 (JTAG) Boundary-scan 26.1 Features 26.2 System Overview 26.3 Data Registers 26.3.1 Bypass Register 26.3.2 Device Identification Register 26.3.2.1 Version 26.3.2.2 Part Number 26.3.2.3 Manufacturer ID 26.3.3 Reset Register 26.3.4 Boundary-scan Chain 26.4 Boundary-scan Specific JTAG Instructions 26.4.1 EXTEST; 0x0 26.4.2 IDCODE; 0x1 26.4.3 SAMPLE_PRELOAD; 0x2 26.4.4 AVR_RESET; 0xC 26.4.5 BYPASS; 0xF 26.5 Boundary-scan Related Register in I/O Memory 26.5.1 MCU Control Register – MCUCR 26.5.2 MCU Status Register – MCUSR 26.6 Boundary-scan Chain 26.6.1 Scanning the Digital Port Pins 26.6.2 Scanning the RESET Pin 26.7 Boundary-scan Order 26.8 Boundary-scan Description Language Files 27. Boot Loader Support – Read-While-Write Self-Programming 27.1 Boot Loader Features 27.2 Application and Boot Loader Flash Sections 27.2.1 Application Section 27.2.2 BLS – Boot Loader Section 27.3 Read-While-Write and No Read-While-Write Flash Sections 27.3.1 RWW – Read-While-Write Section 27.3.2 NRWW – No Read-While-Write Section 27.4 Boot Loader Lock Bits 27.5 Entering the Boot Loader Program 27.5.1 Regular Application Conditions 27.5.2 Boot Reset Fuse 27.5.3 External Hardware conditions 27.5.4 Store Program Memory Control and Status Register – SPMCSR 27.6 Addressing the Flash During Self-Programming 27.7 Self-Programming the Flash 27.7.1 Performing Page Erase by SPM 27.7.2 Filling the Temporary Buffer (Page Loading) 27.7.3 Performing a Page Write 27.7.4 Using the SPM Interrupt 27.7.5 Consideration While Updating BLS 27.7.6 Prevent Reading the RWW Section During Self-Programming 27.7.7 Setting the Boot Loader Lock Bits by SPM 27.7.8 EEPROM Write Prevents Writing to SPMCSR 27.7.9 Reading the Fuse and Lock Bits from Software 27.7.10 Reading the Signature Row from Software 27.7.11 Preventing Flash Corruption 27.7.12 Programming Time for Flash when Using SPM 27.7.13 Simple Assembly Code Example for a Boot Loader 27.7.14 Boot Loader Parameters 28. Memory Programming 28.1 Program And Data Memory Lock Bits 28.2 Fuse Bits 28.2.1 Latching of Fuses 28.3 Signature Bytes 28.4 Calibration Byte 28.5 Parallel Programming Parameters, Pin Mapping, and Commands 28.5.1 Signal Names 28.6 Parallel Programming 28.6.1 Enter Programming Mode 28.6.2 Considerations for Efficient Programming 28.6.3 Chip Erase 28.6.4 Programming the Flash 28.6.5 Programming the EEPROM 28.6.6 Reading the Flash 28.6.7 Reading the EEPROM 28.6.8 Programming the Fuse Low Bits 28.6.9 Programming the Fuse High Bits 28.6.10 Programming the Extended Fuse Bits 28.6.11 Programming the Lock Bits 28.6.12 Reading the Fuse and Lock Bits 28.6.13 Reading the Signature Bytes 28.6.14 Reading the Calibration Byte 28.6.15 Parallel Programming Characteristics 28.7 Serial Downloading 28.8 Serial Programming Pin Mapping 28.8.1 Serial Programming Algorithm 28.8.2 Serial Programming Characteristics 28.9 Programming via the JTAG Interface 28.9.1 Programming Specific JTAG Instructions 28.9.2 AVR_RESET (0xC) 28.9.3 PROG_ENABLE (0x4) 28.9.4 PROG_COMMANDS (0x5) 28.9.5 PROG_PAGELOAD (0x6) 28.9.6 PROG_PAGEREAD (0x7) 28.9.7 Data Registers 28.9.8 Reset Register 28.9.9 Programming Enable Register 28.9.10 Programming Command Register 28.9.11 Flash Data Byte Register 28.9.12 Programming Algorithm 28.9.13 Entering Programming Mode 28.9.14 Leaving Programming Mode 28.9.15 Performing Chip Erase 28.9.16 Programming the Flash 28.9.17 Reading the Flash 28.9.18 Programming the EEPROM 28.9.19 Reading the EEPROM 28.9.20 Programming the Fuses 28.9.21 Programming the Lock Bits 28.9.22 Reading the Fuses and Lock Bits 28.9.23 Reading the Signature Bytes 28.9.24 Reading the Calibration Byte 29. Electrical Characteristics 29.1 Absolute Maximum Ratings* 29.2 DC Characteristics 29.3 External Clock Drive Waveforms 29.4 External Clock Drive 29.5 System and Reset Characteristics 29.6 Maximum speed vs. VCC 29.7 2-wire Serial Interface Characteristics 29.8 SPI Timing Characteristics 29.9 Hardware Boot Entrance Timing Characteristics 30. Typical Characteristics 30.1 Active Supply Current 30.2 Idle Supply Current 30.3 Power-down Supply Current 30.4 Power-save Supply Current 30.5 Pin Pull-Up 30.6 Pin Driver Strength 30.7 Pin Threshold and Hysteresis 30.8 BOD Threshold 30.9 Internal Oscillator Speed 30.10 Current Consumption of Peripheral Units 30.11 Current Consumption in Reset and Reset Pulse Width 31. Register Summary 32. Instruction Set Summary 33. Ordering Information 33.1 ATmega16U4 33.2 ATmega32U4 34. Packaging Information 34.1 TQFP44 34.2 QFN44 35. Errata 35.1 ATmega16U4/ATmega32U4 Rev E 35.2 ATmega16U4/ATmega32U4 Rev D 35.3 ATmega16U4/ATmega32U4 Rev C 35.4 ATmega16U4/ATmega32U4 Rev B 35.5 ATmega16U4/ATmega32U4 Rev A 36. Datasheet Revision History for ATmega16U4/ATmega32U4 36.1 Rev. 7766J – 04/2016 36.2 Rev. 7766I – 07/2015 36.3 Rev. 7766H – 06/2014 36.4 Rev. 7766G – 02/2014 36.5 Rev. 7766F – 11/10 36.6 Rev. 7766E – 04/10 36.7 Rev. 7766D – 01/09 36.8 Rev. 7766C – 11/08 36.9 Rev. 7766B – 11/08 36.10 Rev. 7766A – 07/08 Table of Contents