Datasheet Datasheet ATtiny24A, ATtiny44A, ATtiny84A. Summary (Microchip) - 3
| 制造商 | Microchip |
| 描述 | 8-bit Microcontroller with 2K/4K/8K Bytes In-System Programmable Flash |
| 页数 / 页 | 22 / 3 — ATtiny24A/44A/84A. 1.1. Pin Descriptions. 1.1.1. VCC. 1.1.2. GND. 1.1.3. … |
| 文件格式/大小 | PDF / 707 Kb |
| 文件语言 | 英语 |
ATtiny24A/44A/84A. 1.1. Pin Descriptions. 1.1.1. VCC. 1.1.2. GND. 1.1.3. Port B (PB3:PB0). 1.1.4. RESET. 1.1.5. Port A (PA7:PA0)
该数据表的模型线
- ATTINY24A-CCU ATTINY24A-CCUR ATTINY24A-MF ATTINY24A-MFR ATTINY24A-MM8 ATTINY24A-MM8R ATTINY24A-MMH ATTINY24A-MMHR ATTINY24A-MU ATTINY24A-MUR ATTINY24A-PU ATTINY24A-SSF ATTINY24A-SSFR ATTINY24A-SSN ATTINY24A-SSNR ATTINY24A-SSU ATTINY24A-SSUR
文件文字版本
ATtiny24A/44A/84A 1.1 Pin Descriptions 1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny24A/44A/84A as listed in Section 10.2 “Alternate Port Functions” on page 58.
1.1.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The min- imum pulse length is given in Table 20-4 on page 176. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin.
1.1.5 Port A (PA7:PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in “Alternate Port Functions” on page 58.
3
8183FS–AVR–06/12 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB3:PB0) 1.1.4 RESET 1.1.5 Port A (PA7:PA0) 2. Overview 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 6.1 ATtiny24A 6.2 ATtiny44A 6.3 ATtiny84A 7. Packaging Information 7.1 14S1 7.2 14P3 7.3 15CC1 7.4 20M1 7.5 20M2 8. Errata 8.1 ATtiny24A 8.1.1 Rev. H 8.1.2 Rev. G 8.1.3 Rev. F 8.2 ATtiny44A 8.2.1 Rev. G 8.2.2 Rev. F 8.2.3 Rev. E 8.3 ATtiny84A 8.3.1 Rev. C 9. Datasheet Revision History 9.1 Rev. 8183F – 06/12 9.2 Rev. 8183E – 01/12 9.3 Rev. 8183D – 04/11 9.4 Rev. 8183C – 03/11 9.5 Rev. 8183B – 03/10 9.6 Rev. 8183A – 12/08
Supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny24A/44A/84A as listed in Section 10.2 “Alternate Port Functions” on page 58.
1.1.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The min- imum pulse length is given in Table 20-4 on page 176. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin.
1.1.5 Port A (PA7:PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in “Alternate Port Functions” on page 58.
3
8183FS–AVR–06/12 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB3:PB0) 1.1.4 RESET 1.1.5 Port A (PA7:PA0) 2. Overview 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 6.1 ATtiny24A 6.2 ATtiny44A 6.3 ATtiny84A 7. Packaging Information 7.1 14S1 7.2 14P3 7.3 15CC1 7.4 20M1 7.5 20M2 8. Errata 8.1 ATtiny24A 8.1.1 Rev. H 8.1.2 Rev. G 8.1.3 Rev. F 8.2 ATtiny44A 8.2.1 Rev. G 8.2.2 Rev. F 8.2.3 Rev. E 8.3 ATtiny84A 8.3.1 Rev. C 9. Datasheet Revision History 9.1 Rev. 8183F – 06/12 9.2 Rev. 8183E – 01/12 9.3 Rev. 8183D – 04/11 9.4 Rev. 8183C – 03/11 9.5 Rev. 8183B – 03/10 9.6 Rev. 8183A – 12/08