Datasheet ATmega64A - Summary (Microchip)
| 制造商 | Microchip |
| 描述 | 8-bit AVR Micrcontroller |
| 页数 / 页 | 20 / 1 — 8-bit AVR Micrcontroller. ATmega64A. DATASHEET SUMMARY. Introduction. … |
| 文件格式/大小 | PDF / 333 Kb |
| 文件语言 | 英语 |
8-bit AVR Micrcontroller. ATmega64A. DATASHEET SUMMARY. Introduction. Features. This is a summary document. A
该数据表的模型线
文件文字版本
link to page 13
8-bit AVR Micrcontroller ATmega64A DATASHEET SUMMARY Introduction
The Atmel® ATmega64A is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64A achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
Features
• High-performance, Low-power Atmel AVR 8-bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions - Most Single-clock Cycle Execution – 32 × 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 64Kbytes of In-System Self-programmable Flash program memory – 2Kbytes EEPROM – 4Kbytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Up to 64 Kbytes Optional External Memory Space – Programming Lock for Software Security – SPI Interface for In-System Programming
This is a summary document. A
• JTAG (IEEE std. 1149.1 Compliant) Interface
complete document is available on our Web site at
– Boundary-scan Capabilities According to the JTAG Standard
www.atmel.com
– Extensive On-chip Debug Support Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. ATmega103 and ATmega64A Compatibility 5.1. ATmega103 Compatibility Mode 6. Pin Configurations 6.1. Pin Descriptions 6.1.1. VCC 6.1.2. GND 6.1.3. Port A (PA7:PA0) 6.1.4. Port B (PB7:PB0) 6.1.5. Port C (PC7:PC0) 6.1.6. Port D (PD7:PD0) 6.1.7. Port E (PE7:PE0) 6.1.8. Port F (PF7:PF0) 6.1.9. Port G (PG4:PG0) 6.1.10. RESET 6.1.11. XTAL1 6.1.12. XTAL2 6.1.13. AVCC 6.1.14. AREF 6.1.15. PEN 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 11. Packaging Information 11.1. 64A 11.2. 64M1 12. Errata 12.1. ATmega64A Rev. D
8-bit AVR Micrcontroller ATmega64A DATASHEET SUMMARY Introduction
The Atmel® ATmega64A is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64A achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
Features
• High-performance, Low-power Atmel AVR 8-bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions - Most Single-clock Cycle Execution – 32 × 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 64Kbytes of In-System Self-programmable Flash program memory – 2Kbytes EEPROM – 4Kbytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Up to 64 Kbytes Optional External Memory Space – Programming Lock for Software Security – SPI Interface for In-System Programming
This is a summary document. A
• JTAG (IEEE std. 1149.1 Compliant) Interface
complete document is available on our Web site at
– Boundary-scan Capabilities According to the JTAG Standard
www.atmel.com
– Extensive On-chip Debug Support Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. ATmega103 and ATmega64A Compatibility 5.1. ATmega103 Compatibility Mode 6. Pin Configurations 6.1. Pin Descriptions 6.1.1. VCC 6.1.2. GND 6.1.3. Port A (PA7:PA0) 6.1.4. Port B (PB7:PB0) 6.1.5. Port C (PC7:PC0) 6.1.6. Port D (PD7:PD0) 6.1.7. Port E (PE7:PE0) 6.1.8. Port F (PF7:PF0) 6.1.9. Port G (PG4:PG0) 6.1.10. RESET 6.1.11. XTAL1 6.1.12. XTAL2 6.1.13. AVCC 6.1.14. AREF 6.1.15. PEN 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 11. Packaging Information 11.1. 64A 11.2. 64M1 12. Errata 12.1. ATmega64A Rev. D