Datasheet ATtiny212, ATTINY412 (Microchip)

ATtiny212/412 AVR® Microcontroller with Core Independent Peripherals and picoPower® technology Introduction
The ATtiny212/412 microcontrollers are using the high-performance low-power AVR® RISC architecture, and is capable of running at up to 20MHz, with up to 2/4KB Flash, 128/256bytes of SRAM and 64/128bytes of EEPROM in a 8- pin package. The series uses the latest technologies with a flexible and low power architecture including Event System and SleepWalking, accurate analog features and advanced peripherals.
Features
• CPU – AVR® 8-bit CPU – Running at up to 20MHz – Single Cycle I/O Access – Two-level Interrupt Controller – Two-cycle Hardware Multiplier • Memories – 2/4KB In-system self-programmable Flash Memory – 64/128B EEPROM – 128/256B SRAM • System – Power-on Reset (POR) – Brown-out Detection (BOD) – Clock Options: • 16/20MHz Low Power Internal RC Oscillator • 32.768kHz Ultra Low Power (ULP) Internal RC Oscillator • 32.768kHz External Crystal Oscillator • External Clock Input – Single Pin Unified Program Debug Interface (UPDI) – Three Sleep Modes: • Idle with All Peripherals Running and Mode for Immediate Wake Up Time • Standby – Configurable Operation of Selected Peripherals – SleepWalking Peripherals • Power Down with Wake-up Functionality • Peripherals © 2017 Microchip Technology Inc.
Datasheet Preliminary
DS40001911A-page 1 Document Outline Introduction Features Table of Contents 1. tinyAVR® 1-Series Overview 1.1. Configuration Summary 1.1.1. Peripheral Summary 2. Ordering Information 2.1. ATtiny212 2.2. ATtiny412 3. Block Diagram 4. Pinout 4.1. 8-pin SOIC 5. I/O Multiplexing and Considerations 5.1. Multiplexed Signals 6. Memories 6.1. Overview 6.2. Memory Map 6.3. In-System Reprogrammable Flash Program Memory 6.4. SRAM Data Memory 6.5. EEPROM Data Memory 6.6. User Row 6.7. Signature Bytes 6.8. I/O Memory 6.8.1. Register Summary - GPIOR 6.8.2. Register Description - GPIOR 6.8.2.1. General Purpose I/O register n 6.9. FUSES - Configuration and User Fuses 6.9.1. Signature Row Summary - SIGROW 6.9.2. Signature Row Description 6.9.2.1. Device ID n 6.9.2.2. Serial Number Byte n 6.9.2.3. Temperature Sensor Calibration n 6.9.2.4. OSC16 error at 3V 6.9.2.5. OSC16 error at 5V 6.9.2.6. OSC20 error at 3V 6.9.2.7. OSC20 error at 5V 6.9.3. Fuse Summary - FUSE 6.9.4. Fuse Description 6.9.4.1. Watchdog Configuration 6.9.4.2. BOD Configuration 6.9.4.3. Oscillator Configuration 6.9.4.4. Timer Counter Type D Configuration 6.9.4.5. System Configuration 0 6.9.4.6. System Configuration 1 6.9.4.7. Application Code End 6.9.4.8. Boot End 6.9.4.9. Lock Bits 7. Peripherals and Architecture 7.1. Peripheral Module Address Map 7.2. Interrupt Vector Mapping 7.3. SYSCFG - System Configuration 7.3.1. Register Summary - SYSCFG 7.3.2. Register Description - SYSCFG 7.3.2.1. Device Revision ID Register 8. AVR CPU 8.1. Features 8.2. Overview 8.3. Architecture 8.4. ALU - Arithmetic Logic Unit 8.4.1. Hardware Multiplier 8.5. Functional Description 8.5.1. Program Flow 8.5.2. Instruction Execution Timing 8.5.3. Status Register 8.5.4. Stack and Stack Pointer 8.5.5. Register File 8.5.5.1. The X-, Y-, and Z- Registers 8.5.6. Accessing 16-bit Registers 8.5.7. CCP - Configuration Change Protection 8.5.7.1. Sequence for Write Operation to Configuration Change Protected I/O Registers 8.5.7.2. Sequence for Execution of Self-Programming 8.6. Register Summary - CPU 8.7. Register Description 8.7.1. Configuration Change Protection 8.7.2. Stack Pointer 8.7.3. Status Register 9. NVMCTRL - Non Volatile Memory Controller 9.1. Features 9.2. Overview 9.2.1. Block Diagram 9.2.2. System Dependencies 9.2.2.1. Clocks 9.2.2.2. I/O Lines and Connections 9.2.2.3. Interrupts 9.2.2.4. Events 9.2.2.5. Debug Operation 9.3. Functional Description 9.3.1. Memory Organization 9.3.1.1. Flash 9.3.1.2. EEPROM 9.3.1.3. User Row 9.3.2. Memory Access 9.3.2.1. Read 9.3.2.2. Page Buffer Load 9.3.2.3. Programming 9.3.2.4. Commands 9.3.2.4.1. Write Command 9.3.2.4.2. Erase Command 9.3.2.4.3. Erase-Write Operation 9.3.2.4.4. Page Buffer Clear Command 9.3.2.4.5. Chip Erase Command 9.3.2.4.6. EEPROM Erase Command 9.3.2.4.7. Fuse Write Command 9.3.3. Preventing Flash/EEPROM Corruption 9.3.4. Interrupts 9.3.5. Sleep Mode Operation 9.3.6. Configuration Change Protection 9.4. Register Summary - NVMCTRL 9.5. Register Description 9.5.1. Control A 9.5.2. Control B 9.5.3. Status 9.5.4. Interrupt Control 9.5.5. Interrupt Flags 9.5.6. Data 9.5.7. Address 10. CLKCTRL - Clock Controller 10.1. Features 10.2. Overview 10.2.1. Block Diagram - CLKCTRL 10.2.2. Signal Description 10.3. Functional Description 10.3.1. Sleep Mode Operation 10.3.2. Main Clock Selection and Prescaler 10.3.3. Main Clock after Reset 10.3.4. Clock Sources 10.3.4.1. Internal Oscillators 10.3.4.1.1. 16/20MHz Oscillator (OSC20M) 10.3.4.1.1.1. OSC20M Stored Frequency Error Compensation 10.3.4.1.2. 32KHz Oscillator (OSCULP32K) 10.3.4.2. External Clock Sources 10.3.4.2.1. 32.768kHz Crystal Oscillator (XOSC32K) 10.3.4.2.2. External Clock (EXTCLK) 10.3.5. Configuration Change Protection 10.4. Register Summary - CLKCTRL 10.5. Register Description 10.5.1. Main Clock Control A 10.5.2. Main Clock Control B 10.5.3. Main Clock Lock 10.5.4. Main Clock Status 10.5.5. 16/20MHz Oscillator Control A 10.5.6. 16/20MHz Oscillator Calibration A 10.5.7. 16/20MHz Oscillator Calibration B 10.5.8. 32KHz Oscillator Control A 10.5.9. 32.768kHz Crystal Oscillator Control A 11. SLPCTRL - Sleep Controller 11.1. Features 11.2. Overview 11.2.1. Block Diagram 11.2.2. System Dependencies 11.2.2.1. Clocks 11.2.2.2. I/O Lines and Connections 11.2.2.3. Interrupts 11.2.2.4. Events 11.2.2.5. Debug Operation 11.3. Functional Description 11.3.1. Initialization 11.3.2. Operation 11.3.2.1. Sleep Modes 11.3.2.2. Wake-Up Time 11.3.3. Configuration Change Protection 11.4. Register Summary - SLPCTRL 11.5. Register Description 11.5.1. Control A 12. RSTCTRL - Reset Controller 12.1. Features 12.2. Overview 12.2.1. Block Diagram 12.2.2. Signal Description 12.3. Functional Description 12.3.1. Initialization 12.3.2. Operation 12.3.2.1. Reset Sources 12.3.2.1.1. Power-On Reset (POR) 12.3.2.1.2. Brownout Detector (BOD) Reset Source 12.3.2.1.3. Software Reset 12.3.2.1.4. External Reset 12.3.2.1.5. Watchdog Reset 12.3.2.1.6. Universal Program Debug Interface (UPDI) Reset 12.3.2.2. Reset time 12.3.3. Sleep Mode Operation 12.3.4. Configuration Change Protection 12.4. Register Summary - RSTCTRL 12.5. Register Description 12.5.1. Reset Flag Register 12.5.2. Software Reset Register 13. CPUINT - CPU Interrupt Controller 13.1. Features 13.2. Overview 13.2.1. Block Diagram 13.2.2. Signal Description 13.2.3. System Dependencies 13.2.3.1. Clocks 13.2.3.2. I/O Lines and Connections 13.2.3.3. Interrupts 13.2.3.4. Events 13.2.3.5. Debug Operation 13.3. Functional Description 13.3.1. Initialization 13.3.2. Operation 13.3.2.1. Enabling, Disabling, and Resetting 13.3.2.2. Interrupt Vector Locations 13.3.2.3. Interrupt Response Time 13.3.2.4. Interrupt Level 13.3.2.5. Interrupt Priority 13.3.2.5.1. NMI - Non-Maskable Interrupts 13.3.2.5.2. Static Priority 13.3.2.5.3. Round-Robin Scheduling 13.3.2.5.4. Compact Vector Table 13.3.3. Events 13.3.4. Sleep Mode Operation 13.3.5. Configuration Change Protection 13.4. Register Summary - CPUINT 13.5. Register Description 13.5.1. Control A 13.5.2. Status 13.5.3. Interrupt Priority Level 0 13.5.4. Interrupt Vector with Priority Level 1 14. EVSYS - Event System 14.1. Features 14.2. Overview 14.2.1. Block Diagram 14.2.2. Signal Description 14.2.3. System Dependencies 14.2.3.1. Clocks 14.2.3.2. I/O Lines 14.3. Functional Description 14.3.1. Initialization 14.3.2. Operation 14.3.2.1. Event User Multiplexer Setup 14.3.2.2. Event System Channel 14.3.2.3. Event Generators 14.3.2.4. Software Event 14.3.3. Interrupts 14.3.4. Sleep Mode Operation 14.3.5. Debug Operation 14.3.6. Synchronization 14.3.7. Configuration Change Protection 14.4. Register Summary - EVSYS 14.5. Register Description 14.5.1. Asynchronous Channel Strobe 14.5.2. Synchronous Channel Strobe 14.5.3. Asynchronous Channel n Generator Selection 14.5.4. Synchronous Channel n Generator Selection 14.5.5. Asynchronous User Channel n Input Selection 14.5.6. Synchronous User Channel n Input Selection 15. PORTMUX - Port Multiplexer 15.1. Overview 15.2. Register Summary - PORTMUX 15.3. Register Description 15.3.1. Control A 15.3.2. Control B 16. PORT - I/O Pin Configuration 16.1. Features 16.2. Overview 16.2.1. Block Diagram 16.2.2. Signal Description 16.2.3. System Dependencies 16.2.3.1. Clocks 16.2.3.2. I/O Lines and Connections 16.2.3.3. Interrupts 16.2.3.4. Events 16.2.3.5. Debug Operation 16.3. Functional Description 16.3.1. Initialization 16.3.2. Operation 16.3.2.1. Basic Functions 16.3.2.2. Virtual Ports 16.3.2.3. Pin Configuration 16.3.3. Interrupts 16.3.4. Sleep Mode Operation 16.3.5. Synchronization 16.3.6. Configuration Change Protection 16.4. Register Summary - PORT 16.5. Register Description - Ports 16.5.1. Data Direction 16.5.2. Data Direction Set 16.5.3. Data Direction Clear 16.5.4. Data Direction Toggle 16.5.5. Output Value 16.5.6. Output Value Set 16.5.7. Output Value Clear 16.5.8. Output Value Toggle 16.5.9. Input Value 16.5.10. Interrupt Flags 16.5.11. Pin n Control 16.6. Register Summary - VPORT 16.7. Register Description - Virtual Ports 16.7.1. Data Direction 16.7.2. Output Value 16.7.3. Input Value 16.7.4. Interrupt Flag 17. BOD - Brownout Detector 17.1. Features 17.2. Overview 17.2.1. Block Diagram 17.2.2. System Dependencies 17.2.2.1. Clocks 17.2.2.2. I/O Lines and Connections 17.2.2.3. Interrupts 17.2.2.4. Events 17.2.2.5. Debug Operation 17.3. Functional Description 17.3.1. Initialization 17.3.2. Interrupts 17.3.3. Sleep Mode Operation 17.3.4. Synchronization 17.3.5. Configuration Change Protection 17.4. Register Summary - BOD 17.5. Register Description 17.5.1. Control A 17.5.2. Control B 17.5.3. VLM Control A 17.5.4. Interrupt Control 17.5.5. VLM Interrupt Flags 17.5.6. VLM Status 18. VREF - Voltage Reference 18.1. Features 18.2. Overview 18.2.1. Block Diagram 18.3. Functional Description 18.3.1. Initialization 18.4. Register Summary - VREF 18.5. Register Description 18.5.1. Control A 18.5.2. Control B 19. WDT - Watchdog Timer 19.1. Features 19.2. Overview 19.2.1. Block Diagram 19.2.2. Signal Description 19.2.3. System Dependencies 19.2.3.1. Clocks 19.2.3.2. I/O Lines and Connections 19.2.3.3. Interrupts 19.2.3.4. Events 19.2.3.5. Debug Operation 19.3. Functional Description 19.3.1. Initialization 19.3.2. Operation 19.3.2.1. Normal Mode 19.3.2.2. Window Mode 19.3.2.3. Configuration Protection and Lock 19.3.3. Events 19.3.4. Interrupts 19.3.5. Sleep Mode Operation 19.3.6. Synchronization 19.3.7. Configuration Change Protection 19.4. Register Summary - WDT 19.5. Register Description 19.5.1. Control A 19.5.2. Status 20. TCA - 16-bit Timer/Counter Type A 20.1. Features 20.2. Overview 20.2.1. Block Diagram 20.2.2. Signal Description 20.2.3. System Dependencies 20.2.3.1. Clocks 20.2.3.2. I/O Lines and Connections 20.2.3.3. Interrupts 20.2.3.4. Events 20.2.3.5. Debug Operation 20.3. Functional Description 20.3.1. Definitions 20.3.2. Initialization 20.3.3. Operation 20.3.3.1. Normal Operation 20.3.3.2. Double Buffering 20.3.3.3. Changing the Period 20.3.3.4. Compare Channel 20.3.3.4.1. Waveform Generation 20.3.3.4.2. Frequency (FRQ) Waveform Generation 20.3.3.4.3. Single-Slope PWM Generation 20.3.3.4.4. Dual-slope PWM 20.3.3.4.5. Port Override for Waveform Generation 20.3.3.5. Timer/Counter Commands 20.3.3.6. Split Mode - Two 8-Bit Timer/Counters 20.3.4. Events 20.3.5. Interrupts 20.3.6. Sleep Mode Operation 20.3.7. Configuration Change Protection 20.4. Register Summary - TCA in Normal Mode (CTRLD.SPLITM=0) 20.5. Register Description - Normal Mode 20.5.1. Control A 20.5.2. Control B - Normal Mode 20.5.3. Control C - Normal Mode 20.5.4. Control D 20.5.5. Control Register E Clear - Normal Mode 20.5.6. Control Register E Set - Normal Mode 20.5.7. Control Register F Clear 20.5.8. Control Register F Set 20.5.9. Event Control 20.5.10. Interrupt Control Register - Normal Mode 20.5.11. Interrupt Flag Register - Normal Mode 20.5.12. Debug Control Register 20.5.13. Temporary bits for 16-bit Access 20.5.14. Counter Register - Normal Mode 20.5.15. Period Register - Normal Mode 20.5.16. Compare n Register - Normal Mode 20.5.17. Period Buffer Register 20.5.18. Compare n Buffer Register 20.6. Register Summary - TCA in Split Mode (CTRLD.SPLITM=1) 20.7. Register Description - Split Mode 20.7.1. Control A 20.7.2. Control B - Split Mode 20.7.3. Control C - Split Mode 20.7.4. Control D 20.7.5. Control Register E Clear - Split Mode 20.7.6. Control Register E Set - Split Mode 20.7.7. Interrupt Control Register - Split Mode 20.7.8. Interrupt Flag Register - Split Mode 20.7.9. Debug Control Register 20.7.10. Low-byte Timer Counter Register - Split Mode 20.7.11. High-byte Timer Counter Register - Split Mode 20.7.12. Low-byte Timer Period Register - Split Mode 20.7.13. High-byte Period Register - Split Mode 20.7.14. Compare Register n for low-byte Timer - Split Mode 20.7.15. High-byte Compare Register n - Split Mode 21. TCB - 16-bit Timer/Counter Type B 21.1. Features 21.2. Overview 21.2.1. Block Diagram 21.2.1.1. Noise Canceler 21.2.2. Signal Description 21.2.3. System Dependencies 21.2.3.1. Clocks 21.2.3.2. I/O Lines and Connections 21.2.3.3. Interrupts 21.2.3.4. Events 21.2.3.5. Debug Operation 21.3. Functional Description 21.3.1. Definitions 21.3.2. Initialization 21.3.3. Operation 21.3.3.1. Modes 21.3.3.1.1. Periodic Interrupt Mode 21.3.3.1.2. Timeout Check Mode 21.3.3.1.3. Input Capture on Event Mode 21.3.3.1.4. Input Capture Frequency Measurement Mode 21.3.3.1.5. Input Capture Pulse Width Measurement Mode 21.3.3.1.6. Input Capture Frequency and Pulse Width Measurement Mode 21.3.3.1.7. Single Shot Mode 21.3.3.1.8. 8-bit PWM Mode 21.3.3.2. Output 21.3.3.3. Noise Canceler 21.3.3.4. Synchronized with TCA0 21.3.4. Events 21.3.5. Interrupts 21.3.6. Sleep Mode Operation 21.3.7. Synchronization 21.3.8. Configuration Change Protection 21.4. Register Summary - TCB 21.5. Register Description 21.5.1. Control A 21.5.2. Control B 21.5.3. Event Control 21.5.4. Interrupt Control 21.5.5. Interrupt Flags 21.5.6. Status 21.5.7. Debug Control 21.5.8. Temporary Value 21.5.9. Count 21.5.10. Capture/Compare 22. TCD - 12-bit Timer/Counter Type D 22.1. Features 22.2. Overview 22.2.1. Block Diagram 22.2.2. Signal Description 22.2.3. System Dependencies 22.2.3.1. Clocks 22.2.3.2. I/O Lines and Connections 22.2.3.3. Interrupts 22.2.3.4. Events 22.2.3.5. Debug Operation 22.2.4. Definitions 22.3. Functional Description 22.3.1. Initialization and Disabling 22.3.2. Operation 22.3.2.1. Register Synchronization Categories 22.3.2.2. Clock Selection and Prescalers 22.3.2.3. Waveform Generation Modes 22.3.2.3.1. One Ramp Mode 22.3.2.3.2. Two Ramp Mode 22.3.2.3.3. Four Ramp Mode 22.3.2.3.4. Dual Slope Mode 22.3.2.4. TCD Inputs 22.3.2.4.1. Input Blanking 22.3.2.4.2. Digital Filter 22.3.2.4.3. Asynchronous Event Detection 22.3.2.4.4. Input Modes 22.3.2.4.4.1. Input Mode 1: Stop Output, Jump to Opposite Compare Cycle and Wait 22.3.2.4.4.2. Input Mode 2: Stop Output, Execute Opposite Compare Cycle and Wait 22.3.2.4.4.3. Input Mode 3: Stop Output, Execute Opposite Compare Cycle while Fault Active 22.3.2.4.4.4. Input Mode 4: Stop all Outputs, Maintain Frequency 22.3.2.4.4.5. Input Mode 5: Stop all Outputs, Execute Dead Time while Fault Active 22.3.2.4.4.6. Input Mode 6: Stop all Outputs, Jump to next Compare Cycle and Wait 22.3.2.4.4.7. Input Mode 7: Stop all Outputs, Wait for Software Action 22.3.2.4.4.8. Input Mode 8: Stop Output on Edge, Jump to Next Compare Cycle 22.3.2.4.4.9. Input Mode 9: Stop Output at Level, Maintain Frequency 22.3.2.4.4.10. Input Mode 10: Stop Output on Edge, Maintain Frequency 22.3.2.4.4.11. Input Mode Summary 22.3.2.5. Dithering 22.3.2.6. TCD Counter Capture 22.3.2.7. Output Control 22.3.3. Events 22.3.3.1. Programmable output events 22.3.4. Interrupts 22.3.5. Sleep Mode Operation 22.3.6. Synchronization 22.3.7. Configuration Change Protection 22.4. Register Summary - TCD 22.5. Register Description 22.5.1. Control A 22.5.2. Control B 22.5.3. Control C 22.5.4. Control D 22.5.5. Control E 22.5.6. Event Control x 22.5.7. Interrupt Control 22.5.8. Interrupt Flags 22.5.9. Status 22.5.10. Input Control x 22.5.11. Fault Control 22.5.12. Delay Control 22.5.13. Delay Value 22.5.14. Dither Control 22.5.15. Dither Value 22.5.16. Debug Control 22.5.17. Capture x 22.5.18. Compare Set x 22.5.19. Compare Clear x 23. RTC - Real Time Counter 23.1. Features 23.2. Overview 23.2.1. Block Diagram 23.2.2. Signal Description 23.2.3. System Dependencies 23.2.3.1. Clocks 23.2.3.2. I/O Lines and Connections 23.2.3.3. Interrupts 23.2.3.4. Events 23.2.3.5. Debug Operation 23.3. RTC Functional Description 23.3.1. Initialization 23.3.1.1. Configure the clock CLK_RTC 23.3.1.2. Configure RTC 23.3.2. Operation - RTC 23.3.2.1. Enabling, Disabling, and Resetting 23.4. PIT Functional Description 23.4.1. Initialization 23.4.2. Operation - PIT 23.4.2.1. Enabling, Disabling, and Resetting 23.5. Events 23.6. Interrupts 23.7. Sleep Mode Operation 23.8. Synchronization 23.9. Configuration Change Protection 23.10. Register Summary - RTC 23.11. Register Description 23.11.1. Control A 23.11.2. Status 23.11.3. Interrupt Control 23.11.4. Interrupt Flag 23.11.5. Temporary 23.11.6. Debug Control 23.11.7. Clock Selection 23.11.8. Count 23.11.9. Period 23.11.10. Compare 23.11.11. Periodic Interrupt Timer Control A 23.11.12. Periodic Interrupt Timer Status 23.11.13. PIT Interrupt Control 23.11.14. PIT Interrupt Flag 23.11.15. Periodic Interrupt Timer Debug Control 24. USART - Universal Synchronous and Asynchronous Receiver and Transmitter 24.1. Features 24.2. Overview 24.2.1. Signal Description 24.2.2. System Dependencies 24.2.2.1. Clocks 24.2.2.2. I/O Lines and Connections 24.2.2.3. Interrupts 24.2.2.4. Events 24.2.2.5. Debug Operation 24.2.2.6. Block Diagram 24.3. Functional Description 24.3.1. Initialization 24.3.2. Operation 24.3.2.1. Clock Generation 24.3.2.1.1. Internal Clock Generation - The Fractional Baud Rate Generator 24.3.2.1.2. External Clock 24.3.2.1.3. Double Speed Operation 24.3.2.1.4. Synchronous Clock Operation 24.3.2.1.5. Master SPI Mode Clock Generation 24.3.2.2. Frame Formats 24.3.2.2.1. Parity 24.3.2.2.2. SPI Frame Formats 24.3.2.3. Data Transmission - USART Transmitter 24.3.2.3.1. Sending Frames 24.3.2.3.2. Disabling the Transmitter 24.3.2.4. Data Reception - USART Receiver 24.3.2.4.1. Receiving Frames 24.3.2.4.2. Receiver Error Flags 24.3.2.4.3. Parity Checker 24.3.2.4.4. Disabling the Receiver 24.3.2.4.5. Flushing the Receive Buffer 24.3.2.4.6. Asynchronous Data Reception 24.3.2.4.6.1. Asynchronous Clock Recovery 24.3.2.4.6.2. Asynchronous Data Recovery 24.3.2.4.7. Asynchronous Operational Range 24.3.2.5. USART in Master SPI mode 24.3.2.5.1. USART SPI vs. SPI 24.3.2.6. RS485 Mode of Operation 24.3.2.7. Start Frame Detection 24.3.2.8. Break Character Detection and Auto-baud 24.3.2.9. One-wire Mode 24.3.2.10. Multiprocessor Communication Mode 24.3.2.10.1. Using Multiprocessor Communication Mode 24.3.2.11. IRCOM Mode of Operation 24.3.2.11.1. Overview 24.3.2.11.2. Block Diagram 24.3.2.11.3. IRCOM and Event System 24.3.3. Events 24.3.4. Interrupts 24.3.5. Configuration Change Protection 24.4. Register Summary - USART 24.5. Register Description 24.5.1. Receiver Data Register Low Byte 24.5.2. Receiver Data Register High Byte 24.5.3. Transmit Data Register Low Byte 24.5.4. Transmit Data Register High Byte 24.5.5. USART Status Register 24.5.6. Control A 24.5.7. Control B 24.5.8. Control C - Async Mode 24.5.9. Control C - Master SPI Mode 24.5.10. Baud Register 24.5.11. Debug Control Register 24.5.12. IrDA Control Register 24.5.13. IRCOM Transmitter Pulse Length Control Register 24.5.14. IRCOM Receiver Pulse Length Control Register 25. SPI - Serial Peripheral Interface 25.1. Features 25.2. Overview 25.2.1. Block Diagram 25.2.2. Signal Description 25.2.3. System Dependencies 25.2.3.1. Clocks 25.2.3.2. I/O Lines and Connections 25.2.3.3. Interrupts 25.2.3.4. Events 25.2.3.5. Debug Operation 25.3. Functional Description 25.3.1. Initialization 25.3.2. Operation 25.3.2.1. Master Mode Operation 25.3.2.1.1. SS Pin Functionality in Master Mode - Multimaster support 25.3.2.1.2. Normal Mode 25.3.2.1.3. Buffer Mode 25.3.2.2. Slave Mode 25.3.2.2.1. SS Pin Functionality in Slave Mode 25.3.2.2.2. Normal Mode 25.3.2.2.3. Buffer Mode 25.3.2.3. Data Modes 25.3.3. Interrupts 25.3.4. Sleep Mode Operation 25.3.5. Configuration Change Protection 25.4. Register Summary - SPI 25.5. Register Description 25.5.1. Control A 25.5.2. Control B 25.5.3. Interrupt Control 25.5.4. Interrupt Flags 25.5.5. Data 26. TWI - Two Wire Interface 26.1. Features 26.2. Overview 26.2.1. Block Diagram 26.2.2. Signal Description 26.2.3. System Dependencies 26.2.3.1. Clocks 26.2.3.2. I/O Lines and Connections 26.2.3.3. Interrupts 26.2.3.4. Events 26.2.3.5. Debug Operation 26.3. Functional Description 26.3.1. Initialization 26.3.2. General TWI Bus Concepts 26.3.2.1. START and STOP Conditions 26.3.2.2. Bit Transfer 26.3.2.3. Address Packet 26.3.2.4. Data Packet 26.3.2.5. Transaction 26.3.2.6. Clock and Clock Stretching 26.3.2.7. Arbitration 26.3.2.8. Synchronization 26.3.3. TWI Bus State Logic 26.3.4. Operation 26.3.4.1. Electrical Characteristics 26.3.4.2. TWI Master Operation 26.3.4.2.1. Clock Generation 26.3.4.2.2. Transmitting Address Packets 26.3.4.2.2.1. Case M1: Arbitration Lost or Bus Error during Address Packet 26.3.4.2.2.2. Case M2: Address Packet Transmit Complete - Address not Acknowledged by Slave 26.3.4.2.2.3. Case M3: Address Packet Transmit Complete - Direction Bit Cleared 26.3.4.2.2.4. Case M4: Address Packet Transmit Complete - Direction Bit Set 26.3.4.2.3. Transmitting Data Packets 26.3.4.2.4. Receiving Data Packets 26.3.4.2.5. Quick Command Mode 26.3.4.3. TWI Slave Operation 26.3.4.3.1. Receiving Address Packets 26.3.4.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set 26.3.4.3.1.2. Case S2: Address Packet Accepted - Direction Bit Cleared 26.3.4.3.1.3. Case S3: Collision 26.3.4.3.1.4. Case S4: STOP Condition Received 26.3.4.3.2. Receiving Data Packets 26.3.4.3.3. Transmitting Data Packets 26.3.4.4. Smart Mode 26.3.5. Events 26.3.6. Interrupts 26.3.7. Sleep Mode Operation 26.3.8. Synchronization 26.3.9. Configuration Change Protection 26.4. Register Summary - TWI 26.5. Register Description 26.5.1. Control A 26.5.2. Debug Control 26.5.3. Master Control A 26.5.4. Master Control B 26.5.5. Master Status 26.5.6. Master Baud Rate 26.5.7. Master Address 26.5.8. Master DATA 26.5.9. Slave Control A 26.5.10. Slave Control B 26.5.11. Slave Status 26.5.12. Slave Address 26.5.13. Slave Data 26.5.14. Slave Address Mask 27. CRCSCAN - Cyclic Redundancy Check Memory Scan 27.1. Features 27.2. Overview 27.2.1. Block Diagram 27.2.2. System Dependencies 27.2.2.1. Clocks 27.2.2.2. I/O Lines and Connections 27.2.2.3. Interrupts 27.2.2.4. Events 27.2.2.5. Debug Operation 27.3. Functional Description 27.3.1. Initialization 27.3.2. Operation 27.3.2.1. Checksum 27.3.2.2. Background Scan Timing 27.3.3. Interrupts 27.3.4. Sleep Mode Operation 27.3.5. Configuration Change Protection 27.4. Register Summary - CRCSCAN 27.5. Register Description 27.5.1. Control A 27.5.2. Control B 27.5.3. Status 28. CCL – Configurable Custom Logic 28.1. Features 28.2. Overview 28.2.1. Block Diagram 28.2.2. Signal Description 28.2.3. System Dependencies 28.2.3.1. Clocks 28.2.3.2. I/O Lines 28.2.3.3. Interrupts 28.2.3.4. Events 28.2.3.5. Debug Operation 28.3. Functional Description 28.3.1. Initialization 28.3.2. Operation 28.3.2.1. Enabling, Disabling and Resetting 28.3.2.2. Lookup Table Logic 28.3.2.3. Truth Table Inputs Selection 28.3.2.4. Filter 28.3.2.5. Edge Detector 28.3.2.6. Sequential Logic 28.3.2.7. Clock Source Settings 28.3.3. Events 28.3.4. Sleep Mode Operation 28.3.5. Configuration Change Protection 28.4. Register Summary - CCL 28.5. Register Description 28.5.1. Control A 28.5.2. Sequential Control 0 28.5.3. LUT n Control A 28.5.4. LUT n Control B 28.5.5. LUT n Control C 28.5.6. TRUTHn 29. AC – Analog Comparator 29.1. Features 29.2. Overview 29.2.1. Block Diagram 29.2.2. Signal Description 29.2.3. System Dependencies 29.2.3.1. Clocks 29.2.3.2. I/O Lines and Connections 29.2.3.3. Interrupts 29.2.3.4. Events 29.2.3.5. Debug Operation 29.3. Functional Description 29.3.1. Initialization 29.3.2. Operation 29.3.2.1. Input Hysteresis 29.3.2.2. Input Sources 29.3.2.2.1. Pin Inputs 29.3.2.2.2. Internal Inputs 29.3.2.3. Low Power Mode 29.3.3. Events 29.3.4. Interrupts 29.3.5. Sleep Mode Operation 29.3.6. Configuration Change Protection 29.4. Register Summary - AC 29.5. Register Description 29.5.1. Control A 29.5.2. Mux Control A 29.5.3. Interrupt Control 29.5.4. Status 30. ADC - Analog to Digital Converter 30.1. Features 30.2. Overview 30.2.1. Block Diagram 30.2.2. Signal Description 30.2.3. System Dependencies 30.2.3.1. Clocks 30.2.3.2. I/O Lines and Connections 30.2.3.3. Interrupts 30.2.3.4. Events 30.2.3.5. Debug Operation 30.2.4. Definitions 30.3. Functional Description 30.3.1. Initialization 30.3.2. Operation 30.3.2.1. Starting a Conversion 30.3.2.2. Clock generation 30.3.2.3. Conversion timing 30.3.2.4. Changing Channel or Reference Selection 30.3.2.4.1. ADC Input Channels 30.3.2.4.2. ADC Voltage Reference 30.3.2.4.3. Analog Input Circuitry 30.3.2.5. ADC Conversion Result 30.3.2.6. Temperature Measurement 30.3.2.7. Window Comparator Mode 30.3.3. Events 30.3.4. Interrupts 30.3.5. Sleep Mode Operation 30.3.6. Synchronization 30.3.7. Configuration Change Protection 30.4. Register Summary - ADC 30.5. Register Description 30.5.1. Control A 30.5.2. Control B 30.5.3. Control C 30.5.4. Control D 30.5.5. Control E 30.5.6. Sample Control 30.5.7. MUXPOS 30.5.8. Command 30.5.9. Event Control 30.5.10. Interrupt Control 30.5.11. Interrupt Flags 30.5.12. Debug Run 30.5.13. Temporary 30.5.14. Result 30.5.15. Window Comparator Low Threshold 30.5.16. Window Comparator High Threshold 31. DAC - Digital to Analog Converter 31.1. Features 31.2. Overview 31.2.1. Block Diagram 31.2.2. Signal Description 31.2.3. System Dependencies 31.2.3.1. Clocks 31.2.3.2. I/O Lines and Connections 31.2.3.3. Events 31.2.3.4. Interrupts 31.2.3.5. Debug Operation 31.3. Functional Description 31.3.1. Initialization 31.3.2. Operation 31.3.2.1. Enabling, Disabling and Resetting 31.3.2.2. Starting a Conversion 31.3.2.3. DAC as Source For Internal Peripherals 31.3.3. Sleep Mode Operation 31.3.4. Configuration Change Protection 31.4. Register Summary - DAC 31.5. Register Description 31.5.1. Control A 31.5.2. DATA 32. UPDI - Unified Program and Debug Interface 32.1. Features 32.2. Overview 32.2.1. Block Diagram 32.2.2. System Dependencies 32.2.2.1. Clocks 32.2.2.2. I/O Lines and Connections 32.2.2.3. Events 32.2.2.4. Power Management 32.3. Functional Description 32.3.1. Principle of Operation 32.3.1.1. UPDI UART 32.3.1.2. BREAK Character 32.3.2. Operation 32.3.2.1. UPDI Enable with Fuse Override of RESET pin 32.3.2.2. UPDI Enable with 12V Override of RESET pin 32.3.2.3. UPDI Disable 32.3.2.4. Output Enable Timer Protection for GPIO Configuration 32.3.2.5. UPDI Communication Error Handling 32.3.2.6. Direction Change 32.3.3. UPDI Instruction Set 32.3.3.1. LDS - Load Data from Data Space Using Direct Addressing 32.3.3.2. STS - Store Data to Data Space Using Direct Addressing 32.3.3.3. LD - Load Data from Data Space Using Indirect Addressing 32.3.3.4. ST - Store Data from Data Space Using Indirect Addressing 32.3.3.5. LCDS - Load Data from Control and Status Register Space 32.3.3.6. STCS (Store Data to Control and Status register space) 32.3.3.7. REPEAT - Set Instruction Repeat Counter 32.3.3.8. KEY - Set Activation KEY 32.3.4. System Clock Measurement with UPDI 32.3.5. Interbyte Delay 32.3.6. System Information Block 32.3.7. Enabling of KEY Protected Interfaces 32.3.7.1. Chip Erase 32.3.7.2. NVM Programming 32.3.7.3. User Row Programming 32.3.8. Events 32.3.9. Sleep Mode Operation 32.4. Register Summary - UPDI 32.5. Register Description 32.5.1. Status A 32.5.2. Status B 32.5.3. Control A 32.5.4. Control B 32.5.5. ASI Key Status 32.5.6. ASI Reset Request 32.5.7. ASI Control A 32.5.8. ASI System Control A 32.5.9. ASI System Status 32.5.10. ASI CRC Status 33. Electrical Characteristics 33.1. Disclaimer 33.2. Absolute Maximum Ratings 33.3. General Operating Ratings 33.4. Power Consumption 33.5. Wake-Up Time 33.6. Peripherals Power Consumption 33.7. BOD and POR Characteristics 33.8. External Reset Characteristics 33.9. Oscillators and Clocks 33.10. I/O Pin Characteristics 33.11. USART 33.12. SPI 33.13. TWI 33.14. Bandgap and VREF 33.15. ADC 33.16. DAC 33.17. AC 33.18. Programming Time 34. Typical Characteristics 34.1. Power Consumption 34.1.1. Supply Currents in Active Mode 34.1.2. Supply Currents in Idle Mode 34.1.3. Supply Currents in Power Down Mode 34.1.4. Supply Currents in Standby Mode 34.2. GPIO 34.3. VREF Characteristics 34.4. BOD Characteristics 34.5. ADC Characteristics 34.6. AC Characteristics 34.7. OSC20M Characteristics 34.8. OSCULP32K Characteristics 35. Packaging Information 35.1. Package Drawings 35.1.1. 8-pin SOIC150 35.2. Thermal Considerations 35.2.1. Thermal Resistance Data 35.2.2. Junction Temperature 36. Instruction Set Summary 37. Conventions 37.1. Numerical Notation 37.2. Memory Size and Type 37.3. Frequency and Time 37.4. Registers and Bits 38. Acronyms and Abbreviations 39. Errata 39.1. Errata - ATtiny212/ATtiny412 39.1.1. Die Revision A 39.1.1.1. AC 39.1.1.2. ADC 39.1.1.3. TCB 39.1.1.4. TWI 39.1.1.5. USART 40. Datasheet Revision History 40.1. Rev. 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