Datasheet MCP4801, MCP4811, MCP4821 (Microchip) - 2

link to page 15
MCP4801/4811/4821 Package Types
PDIP, SOIC, MSOP DFN (2x3)* VDD 1 8 V V OUT DD 1 8 VOUT CS 2 7 VSS CS 2 7 VSS 9 SCK 3
P48X1
6 SHDN SCK 3 6 SHDN
C
SDI 4
M
5 LDAC SDI 4 5 LDAC
MCP4801
: 8-bit single DAC
MCP4811
: 10-bit single DAC
MCP4821
: 12-bit single DAC * Includes Exposed Thermal Pad (EP); see Table 3-1.
Block Diagram
LDAC CS SDI SCK Interface Logic V Power-on DD Reset Input Register VSS DAC VREF Register (2.048V) String DAC Gain Output Logic Op Amp Output Logic SHDN VOUT DS22244B-page 2  2010 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: SPI Input Timing Data. 2.0 Typical Performance Curves FIGURE 2-1: DNL vs. Code (MCP4821). FIGURE 2-2: DNL vs. Code and Temperature (MCP4821). FIGURE 2-3: Absolute DNL vs. Temperature (MCP4821). FIGURE 2-4: INL vs. Code and Temperature (MCP4821). FIGURE 2-5: Absolute INL vs. Temperature (MCP4821). FIGURE 2-6: INL vs. Code (MCP4821). FIGURE 2-7: DNL vs. Code and Temperature (MCP4811). FIGURE 2-8: INL vs. Code and Temperature (MCP4811). FIGURE 2-9: DNL vs. Code and Temperature (MCP4801). FIGURE 2-10: INL vs. Code and Temperature (MCP4801). FIGURE 2-11: Full-Scale VOUT vs. Ambient Temperature and VDD. Gain = 1x. FIGURE 2-12: Full-Scale VOUT vs. Ambient Temperature and VDD. Gain = 2x. FIGURE 2-13: Output Noise Voltage Density (VREF Noise Density) vs. Frequency. Gain = 1x. FIGURE 2-14: Output Noise Voltage (VREF Noise Voltage) vs. Bandwidth. Gain = 2x. FIGURE 2-15: IDD vs. Temperature and VDD. FIGURE 2-16: IDD Histogram (VDD = 2.7V). FIGURE 2-17: IDD Histogram (VDD = 5.0V). FIGURE 2-18: Hardware Shutdown Current vs. Temperature and VDD. FIGURE 2-19: Software Shutdown Current vs. Temperature and VDD. FIGURE 2-20: Offset Error vs. Temperature and VDD. FIGURE 2-21: Gain Error vs. Temperature and VDD. FIGURE 2-22: VIN High Threshold vs. Temperature and VDD. FIGURE 2-23: VIN Low Threshold vs. Temperature and VDD. FIGURE 2-24: Input Hysteresis vs. Temperature and VDD. FIGURE 2-25: VOUT High Limit vs.Temperature and VDD. FIGURE 2-26: VOUT Low Limit vs. Temperature and VDD. FIGURE 2-27: IOUT High Short vs. Temperature and VDD. FIGURE 2-28: IOUT vs. VOUT. Gain = 2x. FIGURE 2-29: VOUT Rise Time. FIGURE 2-30: VOUT Fall Time. FIGURE 2-31: VOUT Rise Time. FIGURE 2-32: VOUT Rise Time. FIGURE 2-33: VOUT Rise Time Exit Shutdown. FIGURE 2-34: PSRR vs. Frequency. 3.0 Pin descriptions TABLE 3-1: Pin Function Table for MCP4801/4811/4821 3.1 Supply Voltage Pins (VDD, VSS) 3.2 Chip Select (CS) 3.3 Serial Clock Input (SCK) 3.4 Serial Data Input (SDI) 3.5 Latch DAC Input (LDAC) 3.6 Analog Output (VOUT) 3.7 Exposed Thermal Pad (EP) 4.0 General Overview TABLE 4-1: LSb of each device FIGURE 4-1: Example for INL Error. FIGURE 4-2: Example for DNL Error. 4.1 Circuit Descriptions FIGURE 4-3: Typical Transient Response. FIGURE 4-4: Output Stage for Shutdown Mode. 5.0 Serial Interface 5.1 Overview 5.2 Write Command FIGURE 5-1: Write Command for MCP4821 (12-bit DAC). FIGURE 5-2: Write Command for MCP4811 (10-bit DAC). FIGURE 5-3: Write Command for MCP4801 (8-bit DAC). 6.0 Typical Applications 6.1 Digital Interface 6.2 Power Supply Considerations 6.3 Output Noise Considerations FIGURE 6-1: Typical Connection Diagram. 6.4 Layout Considerations 6.5 Single-Supply Operation 6.6 Bipolar Operation 6.7 Selectable Gain and Offset Bipolar Voltage Output 6.8 Designing a Double-Precision DAC 6.9 Building Programmable Current Source 7.0 Development support 7.1 Evaluation & Demonstration Boards 8.0 Packaging Information 8.1 Package Marking Information Corporate Office Atlanta Boston Chicago Cleveland Fax: 216-447-0643 Dallas Detroit Kokomo Toronto Fax: 852-2401-3431 Australia - Sydney China - Beijing China - Shanghai India - Bangalore Korea - Daegu Korea - Seoul Singapore Taiwan - Taipei Fax: 43-7242-2244-393 Denmark - Copenhagen France - Paris Germany - Munich Italy - Milan Spain - Madrid UK - Wokingham Worldwide Sales and Service