Datasheet MCP48FEBXX (Microchip)

MCP48FEBXX 8-/10-/12-Bit Single/Dual Voltage Output Nonvolatile Digital-to-Analog Converters with SPI Interface Features Package Types
• Operating Voltage Range:
MCP48FEBx1
- 2.7V to 5.5V - full specifications
MSOP Single
- 1.8V to 2.7V - reduced device specifications VDD 1 10 SDI • Output Voltage Resolutions: CS 2 9 SCK - 8-bit:
MCP48FEB0X
(256 Steps) VREF0 3 8 SDO V V - 10-bit: 4 7
MCP48FEB1X
(1024 Steps) SS OUT0 NC 5 6 LAT0/HVC - 12-bit:
MCP48FEB2X
(4096 Steps) • Rail-to-Rail Output
MCP48FEBx2
• Fast Settling Time of 7.8 µs (typical)
MSOP
• DAC Voltage Reference Source Options:
Dual
V SDI - Device V DD 1 10 DD CS 2 9 SCK - Externa l VREF pin (buffered or unbuffered) V (
1
) REF 3 8 SDO - Internal Band Gap (1.22V typical) V 4 7 VSS OUT0 OUT1 5 6 LAT0/HVC (
1
) V • Output Gain Options: - Unity (1x)
Note 1:
Associated with both DAC0 and DAC1 - 2x • Nonvolatile Memory (EEPROM):
General Description
- User-programmed Power-on Reset The MCP48FEBXX are Single- and Dual-channel 8-bit, (POR)/Brown-out Reset (BOR) output 10-bit, and 12-bit buffered voltage output setting, recal and device configuration bits Digital-to-Analog Converters (DAC) with nonvolatile - Auto Recall of Saved DAC register setting memory and an SPI serial interface. - Auto Recall of Saved Device Configuration The VREF pin, the device VDD or the internal band gap (Voltage Reference, Gain, Power-Down) voltage can be selected as the DAC’s reference • Power-on/Brown-out Reset Protection voltage. When VDD is selected, VDD is connected • Power-Down Modes: internally to the DAC reference circuit. When the VREF pin is used, the user can select the output buffer’s gain - Disconnects output buffer (High Impedance) to be 1 or 2. When the gain is 2, the V - Selection of V REF pin voltage OUT pull-down resistors should be limited to a maximum of V (100 k or 1 k) DD/2. These devices have an SPI-compatible serial interface. • Low Power Consumption: Write commands are supported up to 20 MHz while - Normal operation: <180 µA (Single), read commands are supported up to 10 MHz. 380 µA (Dual) - Power-down operation: 650 nA typical
Applications
- EEPROM write cycle (1.9 mA maximum) • SPI Interface: • Set Point or Offset Trimming - Supports ‘ • Sensor Calibration 00’ and ‘11’ modes - Up to 20 MHz writes and 10 MHz reads • Low-Power Portable Instrumentation - Input buffers support interfacing to • PC Peripherals low-voltage digital devices • Data Acquisition Systems • Package Types: 10-lead MSOP • Motor Control • Extended Temperature Range: -40°C to +125°C  2015 Microchip Technology Inc. DS20005429B-page 1 Document Outline Features Package Types General Description Applications MCP48FEBX1 Device Block Diagram (Single-Channel Output) MCP48FEBX2 Device Block Diagram (Dual-Channel Output) Device Features 1.0 Electrical Characteristics Absolute Maximum Ratings (†) DC Characteristics DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Notes: 1.1 Reset, Power-Down, and SPI Mode Timing Waveforms and Requirements FIGURE 1-1: Power-on and Brown-out Reset Waveforms. FIGURE 1-2: SPI Power-Down Command Waveforms. TABLE 1-1: RESET and Power-Down Timing FIGURE 1-3: VOUT Settling Time Waveform. TABLE 1-2: VOUT Settling Timing FIGURE 1-4: SPI Timing (Mode = 11) Waveforms. FIGURE 1-5: SPI Timing (Mode = 00) Waveforms. TABLE 1-3: SPI Requirements (Mode = 11) TABLE 1-4: SPI Requirements (Mode = 00) Timing Table Notes: Temperature Specifications 2.0 Typical Performance Curves 3.0 Pin Descriptions TABLE 3-1: MCP48FEBX1 (Single-DAC) Pinout Description TABLE 3-2: MCP48FEBX2 (Dual-DAC) Pinout Description 3.1 Positive Power Supply Input (VDD) 3.2 Voltage Reference Pin (VREF) 3.3 Analog Output Voltage Pin (VOUT) 3.4 No Connect (NC) 3.5 Ground (VSS) 3.6 Latch Pin (LAT)/High-Voltage Command (HVC) 3.7 SPI - Chip Select Pin (CS) 3.8 SPI - Serial Data In Pin (SDI) 3.9 SPI - Serial Data Out Pin (SDO) 3.10 SPI - Serial Clock Pin (SCK) 4.0 General Description 4.1 Power-on Reset/Brown-out Reset (POR/BOR) FIGURE 4-1: Power-on Reset Operation. 4.2 Device Memory TABLE 4-1: Memory Map (x16) TABLE 4-2: Factory Default POR / BOR Values TABLE 4-3: WiperLock™ Technology Configuration Bits - Functional Description Register 4-1: DAC0 and DAC1 Registers (Volatile and Nonvolatile) Register 4-2: Voltage Reference (VREF) Control Register (Volatile and Nonvolatile) (Addresses 08h and 18h) Register 4-3: Power-down Control Register (Volatile and Nonvolatile) (Addresses 09h, 19h) Register 4-4: Gain Control and System Status Register (Volatile) (Address 0Ah) Register 4-5: Gain Control Register (Nonvolatile) (Address 1AH) Register 4-6: DAC Wiperlock Technology Status Register (Volatile) (Address 0Bh) 5.0 DAC Circuitry FIGURE 5-1: MCP48FEBXX DAC Module Block Diagram. 5.1 Resistor Ladder FIGURE 5-2: Resistor Ladder Model Block Diagram. 5.2 Voltage Reference Selection FIGURE 5-3: Resistor Ladder Reference Voltage Selection Block Diagram. FIGURE 5-4: Reference Voltage Selection Implementation Block Diagram. 5.3 Output Buffer/VOUT Operation TABLE 5-1: Output Driver Gain FIGURE 5-5: Output Driver Block Diagram. TABLE 5-2: Theoretical Step Voltage (VS) (1) FIGURE 5-6: VOUT pin Slew Rate. FIGURE 5-7: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). TABLE 5-3: DAC Input Code Vs. Calculated Analog Output (VOUT) (VDD = 5.0V) 5.4 Internal Band Gap TABLE 5-4: VOUT Using Band Gap 5.5 Latch Pin (LAT) FIGURE 5-8: LAT and DAC Interaction. FIGURE 5-9: Example use of LAT pin operation. 5.6 Power-Down Operation FIGURE 5-10: VOUT Power-Down Block Diagram. TABLE 5-5: Power-down bits and Output resistive load TABLE 5-6: DAC Current Sources 5.7 DAC Registers, Configuration Bits, and Status Bits 6.0 SPI Serial Interface Module 6.1 Overview 6.2 SPI Serial Interface 6.3 Communication Data Rates 6.4 POR/BOR FIGURE 6-1: Typical SPI Interface Block Diagram. 6.5 Interface Pins (CS, SCK, SDI, SDO, and LAT/HVC) 7.0 SPI Commands TABLE 7-1: SPI Commands - Number of Clocks TABLE 7-2: Command Bit Overview FIGURE 7-1: 8-Bit SPI Command Format. FIGURE 7-2: 24-bit SPI Command Format. 7.1 Write Command TABLE 7-3: Volatile Memory Addresses FIGURE 7-3: Write Command - SDI and SDO States. FIGURE 7-4: Continuous Write Sequence (Volatile Memory only). FIGURE 7-5: 24-Bit Write Command (C1:C0 = “00”) - SPI Waveform with PIC MCU (Mode 1,1). FIGURE 7-6: 24-Bit Write Command (C1:C0 = “00”) - SPI Waveform with PIC MCU (Mode 0,0). 7.2 Read Command FIGURE 7-7: Read Command - SDI and SDO States. FIGURE 7-8: Continuous-Reads Sequence. FIGURE 7-9: 24-Bit Read Command (C1:C0 = “11”) - SPI Waveform with PIC MCU (Mode 1,1). FIGURE 7-10: 24-Bit Read Command (C1:C0 = “11”) - SPI Waveform with PIC MCU (Mode 0,0). 7.3 Commands to Modify the Device Configuration Bits 7.4 Enable Configuration Bit FIGURE 7-11: Enable Command Sequence. FIGURE 7-12: 8-Bit Enable Command (C1:C0 = “10”) - SPI Waveform with PIC MCU (Mode 1,1). FIGURE 7-13: 8-Bit Enable Command (C1:C0 = “10”) - SPI Waveform with PIC MCU (Mode 0,0). 7.5 Disable Configuration Bit FIGURE 7-14: Disable Command Sequence. FIGURE 7-15: 8-Bit Disable Command (C1:C0 = “01”) - SPI Waveform with PIC MCU (Mode 1,1). FIGURE 7-16: 8-Bit Disable Command (C1:C0 = “01”) - SPI Waveform with PIC MCU (Mode 0,0). 8.0 Typical Applications 8.1 Power Supply Considerations FIGURE 8-1: Bypass Filtering Example Circuit. 8.2 Application Examples FIGURE 8-2: Example Circuit Of Set Point or Threshold Calibration. FIGURE 8-3: Single-Supply “Window” DAC. 8.3 Bipolar Operation FIGURE 8-4: Digitally-Controlled Bipolar Voltage Source Example Circuit. 8.4 Selectable Gain and Offset Bipolar Voltage Output FIGURE 8-5: Bipolar Voltage Source with Selectable Gain and Offset. 8.5 Designing a Double-Precision DAC FIGURE 8-6: Simple Double-Precision DAC using MCP48FEBX2. 8.6 Building Programmable Current Source FIGURE 8-7: Digitally-Controlled Current Source. 8.7 Serial Interface Communication Times TABLE 8-1: Serial Interface Times / Frequencies 8.8 Design Considerations FIGURE 8-8: Typical Microcontroller Connections. TABLE 8-2: Package Footprint(1) 9.0 Development Support 9.1 Development Tools 9.2 Technical Documentation TABLE 9-1: Technical Documentation 10.0 Packaging Information 10.1 Package Marking Information 8-/10-/12-Bit Single/Dual Voltage Output Nonvolatile Digital-to-Analog Converters with SPI Interface Appendix A: Revision History Revision B (September 2015) Revision A (September 2015) Appendix B: Terminology B.1 Resolution B.2 Least Significant Bit (LSb) B.3 Monotonic Operation FIGURE B-1: VW (VOUT). B.4 Full-Scale Error (EFS) B.5 Zero-Scale Error (EZS) B.6 Total Unadjusted Error (ET) B.7 Offset Error (EOS) FIGURE B-2: Offset Error and Zero-Scale Error. B.8 Offset Error Drift (EOSD) B.9 Gain Error (EG) FIGURE B-3: Gain Error and Full-Scale Error Example. B.10 Gain-Error Drift (EGD) B.11 Integral Nonlinearity (INL) FIGURE B-4: INL Accuracy. B.12 Differential Nonlinearity (DNL) FIGURE B-5: DNL Accuracy. B.13 Settling Time B.14 Major-Code Transition Glitch B.15 Digital Feed-through B.16 -3 dB Bandwidth B.17 Power-Supply Sensitivity (PSS) B.18 Power-Supply Rejection Ratio (PSRR) B.19 VOUT Temperature Coefficient B.20 Absolute Temperature Coefficient B.21 Noise Spectral Density Product Identification System Worldwide Sales and Service