Datasheet MCP48FVBXX (Microchip) - 3

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MCP48FVBXX MCP48FVBX2 Device Block Diagram (Dual-Channel Output)
VDD Power-up/ Brown-out Control VSS SDI
Memory (32x16)
SPI Serial Interface Module DAC0 and DAC1 (Vol) SDO VREF (Vol) and SCK Power-down (Vol) Control Logic Gain (Vol) CS Status (Vol) VREF1:VREF0 V and PD1:PD0 DD Gain PD1:PD0 and Op V VREF1:VREF0 Band Gap BG Amp VOUT0 (1.22V) VREF + PD1:PD0 -
(1)
PD1:PD0 V V SS DD k 0 or VREF1:VREF0 st 1k 10 der LAT/HVC si e R Lad VREF1:VREF0 Gain and PD1:PD0 VDD PD1:PD0 and Op Band Gap Amp VOUT1 VREF1:VREF0 (1.22V) intVR1 + PD1:PD0 -
(1 )
PD1:PD0 V V DD SS k r 0 o 1k 10 VREF1:VREF0 st er si dd Re La
Note 1:
If Internal Band Gap is selected, this buffer has a 2x gain, if the G bit = ‘1’, this is a total gain of 4.  2015 Microchip Technology Inc. DS20005466A-page 3 Document Outline 8-/10-/12-Bit Single/Dual Voltage Output Volatile Digital-to-Analog Converters with SPI Interface Features Package Types General Description Applications MCP48FVBX1 Device Block Diagram (Single-Channel Output) MCP48FVBX2 Device Block Diagram (Dual-Channel Output) Device Features 1.0 Electrical Characteristics Absolute Maximum Ratings (†) DC Characteristics DC Notes: 1.1 Reset, Power-Down, and SPI Mode Timing Waveforms and Requirements FIGURE 1-1: Power-on and Brown-out Reset Waveforms. FIGURE 1-2: SPI Power-Down Command Waveforms. TABLE 1-1: RESET and Power-Down Timing FIGURE 1-3: VOUT Settling Time Waveform. TABLE 1-2: VOUT Settling Timing FIGURE 1-4: SPI Timing (Mode = 11) Waveforms. FIGURE 1-5: SPI Timing (Mode = 00) Waveforms. TABLE 1-3: SPI Requirements (Mode = 11) TABLE 1-4: SPI Requirements (Mode = 00) Timing Table Notes: Temperature Specifications 2.0 Typical Performance Curves 3.0 Pin Descriptions TABLE 3-1: MCP48FVBX1 (Single-DAC) Pinout Description TABLE 3-2: MCP48FVBX2 (Dual-DAC) Pinout Description 3.1 Positive Power Supply Input (VDD) 3.2 Voltage Reference Pin (VREF) 3.3 Analog Output Voltage Pin (VOUT) 3.4 No Connect (NC) 3.5 Ground (VSS) 3.6 Latch Pin (LAT)/High-Voltage Command (HVC) 3.7 SPI - Chip Select Pin (CS) 3.8 SPI - Serial Data In Pin (SDI) 3.9 SPI - Serial Data Out Pin (SDO) 3.10 SPI - Serial Clock Pin (SCK) 4.0 General Description 4.1 Power-on Reset/Brown-out Reset (POR/BOR) FIGURE 4-1: Power-on Reset Operation. 4.2 Device Memory TABLE 4-1: Memory Map (x16) TABLE 4-2: FACTORY DEFAULT POR / BOR VALUES Register 4-1: DAC0 and DAC1 Registers Register 4-2: Voltage Reference (VREF) Control Register (Address 08h) Register 4-3: Power-down Control Register (Address 09h) Register 4-4: Gain Control and System Status Register (Address 0Ah) 5.0 DAC Circuitry FIGURE 5-1: MCP48FVBXX DAC Module Block Diagram. 5.1 Resistor Ladder FIGURE 5-2: Resistor Ladder Model Block Diagram. 5.2 Voltage Reference Selection FIGURE 5-3: Resistor Ladder Reference Voltage Selection Block Diagram. FIGURE 5-4: Reference Voltage Selection Implementation Block Diagram. 5.3 Output Buffer/VOUT Operation TABLE 5-1: Output Driver Gain FIGURE 5-5: Output Driver Block Diagram. TABLE 5-2: Theoretical Step Voltage (VS) (1) FIGURE 5-6: VOUT Pin Slew Rate. FIGURE 5-7: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). TABLE 5-3: DAC Input Code Vs. Calculated Analog Output (VOUT) (VDD = 5.0V) 5.4 Internal Band Gap TABLE 5-4: VOUT USING BAND GAP 5.5 Latch Pin (LAT) FIGURE 5-8: LAT and DAC Interaction. FIGURE 5-9: Example Use of LAT Pin Operation. 5.6 Power-Down Operation FIGURE 5-10: VOUT Power-Down Block Diagram. TABLE 5-5: POWER-DOWN BITS AND OUTPUT RESISTIVE LOAD TABLE 5-6: DAC CURRENT SOURCES 5.7 DAC Registers, Configuration Bits, and Status Bits 6.0 SPI Serial Interface Module 6.1 Overview 6.2 SPI Serial Interface 6.3 Communication Data Rates 6.4 POR/BOR FIGURE 6-1: Typical SPI Interface Block Diagram. 6.5 Interface Pins (CS, SCK, SDI, SDO, and LAT/HVC) TABLE 6-1: SCK Frequency 6.6 The SPI Modes 7.0 SPI Commands TABLE 7-1: SPI Commands - Number of Clocks TABLE 7-2: Command Bits Overview FIGURE 7-1: 24-bit SPI Command Format. 7.1 Write Command TABLE 7-3: Volatile Memory Addresses FIGURE 7-2: Write Command - SDI and SDO States. FIGURE 7-3: Continuous Write Sequence. FIGURE 7-4: 24-Bit Write Command (C1:C0 = “00”) - SPI Waveform with PIC MCU (Mode 1,1). FIGURE 7-5: 24-Bit Write Command (C1:C0 = “00”) - SPI Waveform with PIC MCU (Mode 0,0). 7.2 Read Command FIGURE 7-6: Read Command - SDI and SDO States. FIGURE 7-7: Continuous-Reads Sequence. FIGURE 7-8: 24-Bit Read Command (C1:C0 = “11”) - SPI Waveform with PIC MCU (Mode 1,1). FIGURE 7-9: 24-Bit Read Command (C1:C0 = “11”) - SPI Waveform with PIC MCU (Mode 0,0). 8.0 Typical Applications 8.1 Power Supply Considerations FIGURE 8-1: Bypass Filtering Example Circuit. 8.2 Application Examples FIGURE 8-2: Example Circuit Of Set-Point or Threshold Calibration. FIGURE 8-3: Single-Supply “Window” DAC. 8.3 Bipolar Operation FIGURE 8-4: Digitally-Controlled Bipolar Voltage Source Example Circuit. 8.4 Selectable Gain and Offset Bipolar Voltage Output FIGURE 8-5: Bipolar Voltage Source with Selectable Gain and Offset. 8.5 Designing a Double-Precision DAC FIGURE 8-6: Simple Double-Precision DAC using MCP48FVBX2. 8.6 Building Programmable Current Source FIGURE 8-7: Digitally-Controlled Current Source. 8.7 Serial Interface Communication Times TABLE 8-1: Serial Interface Times / Frequencies 8.8 Design Considerations FIGURE 8-8: Typical Microcontroller Connections. TABLE 8-2: Package Footprint (1) 9.0 Development Support 9.1 Development Tools 9.2 Technical Documentation TABLE 9-1: Technical Documentation 10.0 Packaging Information 10.1 Package Marking Information Appendix A: Revision History Appendix B: Terminology B.1 Resolution B.2 Least Significant Bit (LSb) B.3 Monotonic Operation FIGURE B-1: VW (VOUT). B.4 Full-Scale Error (EFS) B.5 Zero-Scale Error (EZS) B.6 Total Unadjusted Error (ET) B.7 Offset Error (EOS) FIGURE B-2: Offset Error and Zero-Scale Error. B.8 Offset Error Drift (EOSD) B.9 Gain Error (EG) FIGURE B-3: Gain Error and Full-Scale Error Example. B.10 Gain-Error Drift (EGD) B.11 Integral Nonlinearity (INL) FIGURE B-4: INL Accuracy. B.12 Differential Nonlinearity (DNL) FIGURE B-5: DNL Accuracy. B.13 Settling Time B.14 Major-Code Transition Glitch B.15 Digital Feedthrough B.16 -3 dB Bandwidth B.17 Power-Supply Sensitivity (PSS) B.18 Power-Supply Rejection Ratio (PSRR) B.19 VOUT Temperature Coefficient B.20 Absolute Temperature Coefficient B.21 Noise Spectral Density Product Identification System Trademarks Worldwide Sales and Service