Datasheet LTC4303 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| 页数 / 页 | 12 / 7 — OPERATIO. Figure 1. Input-Output Connection tPLH. Figure 2. Input-Output … |
| 文件格式/大小 | PDF / 563 Kb |
| 文件语言 | 英语 |
OPERATIO. Figure 1. Input-Output Connection tPLH. Figure 2. Input-Output Connection tPHL. ENABLE. Rise Time Accelerators
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LTC4303
U OPERATIO
OUTPUT SIDE INPUT SIDE INPUT SIDE OUTPUT SIDE 50pF 150pF 50pF 150pF 0.5V/DIV 0.5V/DIV 0.5V/DIV 0.5V/DIV 4303 F01 4303 F02 200ns/DIV 20ns/DIV
Figure 1. Input-Output Connection tPLH Figure 2. Input-Output Connection tPHL
the two sides. This effect is displayed in Figure 1 for a
ENABLE
VCC = 3.3V and a 10k pull-up resistor on each side (50pF When the ENABLE pin is driven below 0.8V with respect on one side and 150pF on the other). Since the output side to the LTC4303’s ground, the backplane side is discon- has less capacitance than the input, it rises faster and the nected from the card side, and the READY pin is internally effective tPLH is negative. pulled low. When the pin is driven above 2V, the part waits There is a propagation delay, tPHL, through the connec- for data transactions on the IN side to be complete and tion circuitry for falling waveforms. Figure 2 shows the for the OUT side to be high (as described in the Start-Up falling edge waveforms. An external driver pulls down section) before connecting the two sides. At this time the the voltage on the side with 50pF capacitance; LTC4303 internal pull-down on READY releases. When ENABLE is pulls down the voltage on the opposite side with a delay low, automatic clocking is disabled. of 80ns. This delay is always positive and is a function of A rising edge on ENABLE after a stuck bus condition has supply voltage, temperature and the pull-up resistors and occurred forces a connection between SDAIN, SDAOUT equivalent bus capacitances on both sides of the bus. The and SCLIN, SCLOUT even if bus idle conditions are not Typical Performance Characteristics section shows tPHL met. At this time the internal 30ms timer is reset but not as a function of temperature and voltage for 10k pull-up disabled. resistors and 100pF equivalent capacitance on both sides of the part. Larger output capacitances translate to longer
Rise Time Accelerators
delays. Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems Once connection has been established, rise time accelerator and adjust setup and hold times accordingly. circuits on all four SDA and SCL pins are activated. These allow the use of larger pull-up resistors, reducing power
READY Digital Output
consumption, or bus capacitance beyond that specifi ed in I2C, while still meeting system rise time requirements. The READY pin provides a digital fl ag which indicates the During positive bus transitions, the LTC4303 switches in status of the connection circuitry described previously in 3.5mA (typical) of current to quickly slew the SDA and the “Connection Circuitry” section. READY is high when SCL lines once their DC voltages exceed 0.8V. Choose a the connection circuitry is active, and pulls low when pull-up resistor so that the bus will rise on its own at a there is not a valid connection. The pin is driven by an rate of at least 0.8V/µs to guarantee activation of the ac- open drain pull-down capable of sinking 3mA while hold- celerators. Rise time accelerators turn off when SDA and ing 0.4V on the pin. Connect a resistor of 10k to VCC to SCL lines are approximately 1V below VCC.The rise time provide the pull-up. accelerators are automatically disabled during automatic clocking. 4303fb 7
U OPERATIO
OUTPUT SIDE INPUT SIDE INPUT SIDE OUTPUT SIDE 50pF 150pF 50pF 150pF 0.5V/DIV 0.5V/DIV 0.5V/DIV 0.5V/DIV 4303 F01 4303 F02 200ns/DIV 20ns/DIV
Figure 1. Input-Output Connection tPLH Figure 2. Input-Output Connection tPHL
the two sides. This effect is displayed in Figure 1 for a
ENABLE
VCC = 3.3V and a 10k pull-up resistor on each side (50pF When the ENABLE pin is driven below 0.8V with respect on one side and 150pF on the other). Since the output side to the LTC4303’s ground, the backplane side is discon- has less capacitance than the input, it rises faster and the nected from the card side, and the READY pin is internally effective tPLH is negative. pulled low. When the pin is driven above 2V, the part waits There is a propagation delay, tPHL, through the connec- for data transactions on the IN side to be complete and tion circuitry for falling waveforms. Figure 2 shows the for the OUT side to be high (as described in the Start-Up falling edge waveforms. An external driver pulls down section) before connecting the two sides. At this time the the voltage on the side with 50pF capacitance; LTC4303 internal pull-down on READY releases. When ENABLE is pulls down the voltage on the opposite side with a delay low, automatic clocking is disabled. of 80ns. This delay is always positive and is a function of A rising edge on ENABLE after a stuck bus condition has supply voltage, temperature and the pull-up resistors and occurred forces a connection between SDAIN, SDAOUT equivalent bus capacitances on both sides of the bus. The and SCLIN, SCLOUT even if bus idle conditions are not Typical Performance Characteristics section shows tPHL met. At this time the internal 30ms timer is reset but not as a function of temperature and voltage for 10k pull-up disabled. resistors and 100pF equivalent capacitance on both sides of the part. Larger output capacitances translate to longer
Rise Time Accelerators
delays. Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems Once connection has been established, rise time accelerator and adjust setup and hold times accordingly. circuits on all four SDA and SCL pins are activated. These allow the use of larger pull-up resistors, reducing power
READY Digital Output
consumption, or bus capacitance beyond that specifi ed in I2C, while still meeting system rise time requirements. The READY pin provides a digital fl ag which indicates the During positive bus transitions, the LTC4303 switches in status of the connection circuitry described previously in 3.5mA (typical) of current to quickly slew the SDA and the “Connection Circuitry” section. READY is high when SCL lines once their DC voltages exceed 0.8V. Choose a the connection circuitry is active, and pulls low when pull-up resistor so that the bus will rise on its own at a there is not a valid connection. The pin is driven by an rate of at least 0.8V/µs to guarantee activation of the ac- open drain pull-down capable of sinking 3mA while hold- celerators. Rise time accelerators turn off when SDA and ing 0.4V on the pin. Connect a resistor of 10k to VCC to SCL lines are approximately 1V below VCC.The rise time provide the pull-up. accelerators are automatically disabled during automatic clocking. 4303fb 7