Datasheet LTC4304 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| 页数 / 页 | 16 / 7 — OPERATION. Start-Up. Input to Output Offset Voltage. Bus Stuck Low … |
| 文件格式/大小 | PDF / 660 Kb |
| 文件语言 | 英语 |
OPERATION. Start-Up. Input to Output Offset Voltage. Bus Stuck Low Timeout. Connection Circuitry
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LTC4304
OPERATION Start-Up
the waveforms on the backplane busses look slightly When the LTC4304 fi rst receives power on its V different than the corresponding card bus waveforms, as CC pin, either during power up or live insertion, it starts in an under described here. voltage lockout (UVLO) state, ignoring any activity on the
Input to Output Offset Voltage
SDA or SCL pins until VCC rises above 2.5V (typical). When a logic low voltage, V During this time, the precharge circuitry is active and LOW1, is driven on any of the LTC4304’s data or clock pins, the LTC4304 regulates the forces 1V through 200K nominal resistors to the SDA voltage on the opposite side of the part (call it V and SCL pins. Because the I/O card is being plugged LOW2) to a slightly higher voltage, as directed by the following into a live backplane, the voltage on the backplane SDA equation: and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the VLOW2 = VLOW1 + 75mV + (VCC/R) • 20Ω (typical) worst-case voltage differential these pins will see at the where R is the bus pull-up resistance in ohms. For ex- moment of connection, therefore minimizing the amount ample, if a device is forcing SDAOUT to 10mV where VCC of disturbance caused by the I/O card. = 3.3V and the pull-up resistor R on SDAIN is 10k, then Once the LTC4304 comes out of UVLO, it assumes that the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 20 SDAIN and SCLIN have been inserted into a live system = 91.6mV(typical). See the Typical Performance Charac- and that SDAOUT and SCLOUT are being powered up at teristics section for curves showing the offset voltage as the same time as itself. Therefore, it looks for either a stop a function of VCC and R. bit or bus idle condition on the input side to indicate the completion of a data transaction. When either one occurs,
Bus Stuck Low Timeout
the part also verifi es that both the SDAOUT and SCLOUT When SDAOUT or SCLOUT is low, an internal timer starts. voltages are high. When all of these conditions are met, The timer is only reset when SDAOUT and SCLOUT are the input-to-output connection circuitry is activated, join- both high. If they do not go high within 30ms (typical), ing the SDA and SCL busses on the I/O card with those FAULT pulls low indicating a bus stuck condition and the on the backplane and READY goes high. connection between SDAIN and SDAOUT, and SCLIN and SCLOUT is broken. After a delay of at least 40µs, the
Connection Circuitry
LTC4304 automatically generates up to 16 clock pulses at Once the connection circuitry is activated, the functionality 8.5kHz (typical) on SCLOUT in an attempt to unstick the of the SDAIN and SDAOUT pins is identical. A low forced bus. When SDAOUT and SCLOUT go high, FAULT is cleared on either pin at any time results in both pin voltages be- and reconnection occurs when the conditions described ing low.
For proper operation, logic low input voltages
in the “Start-Up” section above are satisfi ed.
should be no higher than 0.4V with respect to the ground
When powering up into a bus stuck low condition, the
pin voltage of the LTC4304.
SDAIN and SDAOUT enter connection circuitry joining the SDA and SCL busses on a logic high state only when all devices on both SDAIN the I/O card with those on the backplane is not activated. and SDAOUT release high. The same is true for SCLIN 30ms after UVLO, FAULT pulls low indicating a bus stuck and SCLOUT. This important feature ensures that clock low condition, and automatic clocking takes place as stretching, clock synchronization, arbitration and the ac- described above. knowledge protocol always work, regardless of how the devices in the system are tied to the LTC4304.
Propagation Delays
Another key feature of the connection circuitry is that it During a rising edge, the rise-time on each side is de- provides bidirectional buffering, keeping the backplane termined by the bus pull-up resistor and the equivalent and card capacitances isolated. Because of this isolation, capacitance on the line. If the pull-up resistors are the 4304fa 7
OPERATION Start-Up
the waveforms on the backplane busses look slightly When the LTC4304 fi rst receives power on its V different than the corresponding card bus waveforms, as CC pin, either during power up or live insertion, it starts in an under described here. voltage lockout (UVLO) state, ignoring any activity on the
Input to Output Offset Voltage
SDA or SCL pins until VCC rises above 2.5V (typical). When a logic low voltage, V During this time, the precharge circuitry is active and LOW1, is driven on any of the LTC4304’s data or clock pins, the LTC4304 regulates the forces 1V through 200K nominal resistors to the SDA voltage on the opposite side of the part (call it V and SCL pins. Because the I/O card is being plugged LOW2) to a slightly higher voltage, as directed by the following into a live backplane, the voltage on the backplane SDA equation: and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the VLOW2 = VLOW1 + 75mV + (VCC/R) • 20Ω (typical) worst-case voltage differential these pins will see at the where R is the bus pull-up resistance in ohms. For ex- moment of connection, therefore minimizing the amount ample, if a device is forcing SDAOUT to 10mV where VCC of disturbance caused by the I/O card. = 3.3V and the pull-up resistor R on SDAIN is 10k, then Once the LTC4304 comes out of UVLO, it assumes that the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 20 SDAIN and SCLIN have been inserted into a live system = 91.6mV(typical). See the Typical Performance Charac- and that SDAOUT and SCLOUT are being powered up at teristics section for curves showing the offset voltage as the same time as itself. Therefore, it looks for either a stop a function of VCC and R. bit or bus idle condition on the input side to indicate the completion of a data transaction. When either one occurs,
Bus Stuck Low Timeout
the part also verifi es that both the SDAOUT and SCLOUT When SDAOUT or SCLOUT is low, an internal timer starts. voltages are high. When all of these conditions are met, The timer is only reset when SDAOUT and SCLOUT are the input-to-output connection circuitry is activated, join- both high. If they do not go high within 30ms (typical), ing the SDA and SCL busses on the I/O card with those FAULT pulls low indicating a bus stuck condition and the on the backplane and READY goes high. connection between SDAIN and SDAOUT, and SCLIN and SCLOUT is broken. After a delay of at least 40µs, the
Connection Circuitry
LTC4304 automatically generates up to 16 clock pulses at Once the connection circuitry is activated, the functionality 8.5kHz (typical) on SCLOUT in an attempt to unstick the of the SDAIN and SDAOUT pins is identical. A low forced bus. When SDAOUT and SCLOUT go high, FAULT is cleared on either pin at any time results in both pin voltages be- and reconnection occurs when the conditions described ing low.
For proper operation, logic low input voltages
in the “Start-Up” section above are satisfi ed.
should be no higher than 0.4V with respect to the ground
When powering up into a bus stuck low condition, the
pin voltage of the LTC4304.
SDAIN and SDAOUT enter connection circuitry joining the SDA and SCL busses on a logic high state only when all devices on both SDAIN the I/O card with those on the backplane is not activated. and SDAOUT release high. The same is true for SCLIN 30ms after UVLO, FAULT pulls low indicating a bus stuck and SCLOUT. This important feature ensures that clock low condition, and automatic clocking takes place as stretching, clock synchronization, arbitration and the ac- described above. knowledge protocol always work, regardless of how the devices in the system are tied to the LTC4304.
Propagation Delays
Another key feature of the connection circuitry is that it During a rising edge, the rise-time on each side is de- provides bidirectional buffering, keeping the backplane termined by the bus pull-up resistor and the equivalent and card capacitances isolated. Because of this isolation, capacitance on the line. If the pull-up resistors are the 4304fa 7