Datasheet LTC4307 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| 页数 / 页 | 16 / 3 — The. ELECTRICAL CHARACTERISTICS. denotes the specifi cations which apply … |
| 文件格式/大小 | PDF / 181 Kb |
| 文件语言 | 英语 |
The. ELECTRICAL CHARACTERISTICS. denotes the specifi cations which apply over the full operating
该数据表的模型线
- LTC4307CDD#PBF LTC4307CDD#PBF LTC4307CDD#TRPBF LTC4307CDD#TRPBF LTC4307CMS8#PBF LTC4307CMS8#PBF LTC4307CMS8#TRPBF LTC4307CMS8#TRPBF LTC4307IDD#PBF LTC4307IDD#PBF LTC4307IDD#TRPBF LTC4307IDD#TRPBF LTC4307IMS8#3ZZPBF LTC4307IMS8#3ZZTRPBF LTC4307IMS8#PBF LTC4307IMS8#PBF LTC4307IMS8#TRPBF LTC4307IMS8#TRPBF
文件文字版本
LTC4307
The ELECTRICAL CHARACTERISTICS
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Propagation Delay and Rise-Time Accelerators
tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 70 ns VCC = 3.3V (Notes 2, 3) (Figure 1) tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 10 ns VCC = 3.3V (Notes 2, 3) (Figure 1) tRISE SDA/SCL Transition Time Low to High CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC 30 300 ns = 3.3V (See Notes 3, 4) (Figure 1) tFALL SDA/SCL Transition Time High to Low CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC 30 300 ns = 3.3V (See Notes 3, 4) (Figure 1) IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 3.3V 5 8 mA (Note 5)
Input-Output Connection
VOS Input-Output Offset Voltage 2.7k to VCC on SDA, SCL, VCC = 3.3V, ● 20 60 100 mV Driven SDA/SCL = 0.2V VTHR SDA, SCL Logic Input Threshold Voltage Rising Edge 0.45VCC 0.55VCC 0.65VCC V VHYS SDA, SCL Logic Input Threshold Voltage (Note 3) 50 mV Hysteresis CIN Digital Input Capacitance SDAIN, SDAOUT, (Note 3) 10 pF SCLIN, SCLOUT ILEAK Input Leakage Current SDA, SCL, Pins ● ±5 μA VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, ● 0 0.4 V Driven SDA/SCL = 0.2V, VCC = 2.7V 2.7k to VCC on SDA, SCL, VCC = 3.3V, ● 120 160 205 mV Driven SDA/SCL = 0.1V VILMAX Buffer Input Logic Low Voltage VCC = 3.3V ● 1.2 V
Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer VCC = 3.3V, SDAOUT, SCLOUT = 0V ● 25 30 35 ms
Timing Characteristics
fI2C,MAX I2C Maximum Operating Frequency (Note 3) 400 600 kHz tBUF Bus Free Time Between Stop and Start (Note 3) 1.3 μs Condition tHD,STA Hold Time After (Repeated) Start Condition (Note 3) 100 ns tSU,STA Repeated Start Condition Set-Up Time (Note 3) 0 ns tSU,STO Stop Condition Set-Up Time (Note 3) 0 ns tHD,DATI Data Hold Time Input (Note 3) 0 ns tSU,DAT Data Set-Up Time (Note 3) 100 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
Measure points are 0.3 • VCC and 0.7 • VCC. may cause permanent damage to the device. Exposure to any Absolute
Note 5:
IPULLUP varies with temperature and VCC voltage as shown in the Maximum Rating condition for extended periods may affect device Typical Performance Characteristics section. reliability and lifetime.
Note 6:
ICC test performed with connection circuitry active.
Note 2:
See “Propagation Delays” in the Operations section for a
Note 7:
All currents into pins are positive; all voltages are referenced to discussion of tPHL and tPLH as a function of pull-up resistance and bus GND unless otherwise specifi ed. capacitance.
Note 3:
Determined by design, not tested in production. 4307f 3
The ELECTRICAL CHARACTERISTICS
●
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Propagation Delay and Rise-Time Accelerators
tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 70 ns VCC = 3.3V (Notes 2, 3) (Figure 1) tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 10 ns VCC = 3.3V (Notes 2, 3) (Figure 1) tRISE SDA/SCL Transition Time Low to High CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC 30 300 ns = 3.3V (See Notes 3, 4) (Figure 1) tFALL SDA/SCL Transition Time High to Low CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC 30 300 ns = 3.3V (See Notes 3, 4) (Figure 1) IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 3.3V 5 8 mA (Note 5)
Input-Output Connection
VOS Input-Output Offset Voltage 2.7k to VCC on SDA, SCL, VCC = 3.3V, ● 20 60 100 mV Driven SDA/SCL = 0.2V VTHR SDA, SCL Logic Input Threshold Voltage Rising Edge 0.45VCC 0.55VCC 0.65VCC V VHYS SDA, SCL Logic Input Threshold Voltage (Note 3) 50 mV Hysteresis CIN Digital Input Capacitance SDAIN, SDAOUT, (Note 3) 10 pF SCLIN, SCLOUT ILEAK Input Leakage Current SDA, SCL, Pins ● ±5 μA VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, ● 0 0.4 V Driven SDA/SCL = 0.2V, VCC = 2.7V 2.7k to VCC on SDA, SCL, VCC = 3.3V, ● 120 160 205 mV Driven SDA/SCL = 0.1V VILMAX Buffer Input Logic Low Voltage VCC = 3.3V ● 1.2 V
Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer VCC = 3.3V, SDAOUT, SCLOUT = 0V ● 25 30 35 ms
Timing Characteristics
fI2C,MAX I2C Maximum Operating Frequency (Note 3) 400 600 kHz tBUF Bus Free Time Between Stop and Start (Note 3) 1.3 μs Condition tHD,STA Hold Time After (Repeated) Start Condition (Note 3) 100 ns tSU,STA Repeated Start Condition Set-Up Time (Note 3) 0 ns tSU,STO Stop Condition Set-Up Time (Note 3) 0 ns tHD,DATI Data Hold Time Input (Note 3) 0 ns tSU,DAT Data Set-Up Time (Note 3) 100 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
Measure points are 0.3 • VCC and 0.7 • VCC. may cause permanent damage to the device. Exposure to any Absolute
Note 5:
IPULLUP varies with temperature and VCC voltage as shown in the Maximum Rating condition for extended periods may affect device Typical Performance Characteristics section. reliability and lifetime.
Note 6:
ICC test performed with connection circuitry active.
Note 2:
See “Propagation Delays” in the Operations section for a
Note 7:
All currents into pins are positive; all voltages are referenced to discussion of tPHL and tPLH as a function of pull-up resistance and bus GND unless otherwise specifi ed. capacitance.
Note 3:
Determined by design, not tested in production. 4307f 3