Datasheet LTC4308 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | Low Voltage, Level Shifting Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| 页数 / 页 | 16 / 3 — The. ELECTRICAL CHARACTERISTICS. denotes the specifi cations which apply … |
| 文件格式/大小 | PDF / 172 Kb |
| 文件语言 | 英语 |
The. ELECTRICAL CHARACTERISTICS. denotes the specifi cations which apply over the full operating
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LTC4308
The ELECTRICAL CHARACTERISTICS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tIDLE Bus Idle Time l 55 95 175 μs VTHR_EN ENABLE Threshold Voltage ENABLE Rising Edge l 0.45 0.6 0.75 V VTHR_EN(HYST) ENABLE Threshold Voltage Hysteresis (Note 3) 35 mV IENABLE ENABLE Input Current ENABLE from 0V to VCC l 0.1 ±5 μA tPLH_EN ENABLE Delay Off-On (Figure 1) 95 μs tPHL_EN ENABLE Delay On-Off (Note 3), (Figure 1) 10 ns tPLH_READY READY Delay Off-On (Note 3), (Figure 1) 10 ns tPHL_READY READY Delay On-Off (Note 3), (Figure 1) 10 ns VOL_READY READY Output Low Voltage IREADY = 3mA, VCC = 2.3V l 0.4 V IOFF_READY READY Off Leakage Current VCC = READY = 5.5V l 0.1 ±5 μA
Prop Delay and Rise-Time Accelerators
tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 70 ns (Notes 2, 3), (Figure 1) tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 10 ns (Notes 2, 3), (Figure 1) tRISE SDA/SCL Transition Time Low to High CLOAD = 100pF, 10k to VCC on SDA, SCL, 30 300 ns (Notes 3, 4), (Figure 1) tFALL SDA/SCL Transition Time High to Low CLOAD = 100pF, 10k to VCC on SDA, SCL, 30 300 ns (Notes 3, 4), (Figure 1) IPULLUPAC Transient Boosted Pull-Up Current Positive Transition > 0.8V/μs on SDAOUT, 5 8 mA SCLOUT (Note 5)
Input-Output Connection
VOS Input to Output Offset Voltage (OUT – IN) 2.7k to VCC on SDAOUT, SCLOUT, l 250 300 380 mV SDAIN = SCLIN = 0.2V 2.7k to VCC on SDAOUT, SCLOUT, l 250 350 450 mV SDAIN = SCLIN = 0.4V, VCC = 5.5V Output to Input Offset Voltage (IN – OUT) 2.7k to VCC on SDAIN, SCLIN, l –150 –200 –300 mV SDAOUT = SCLOUT = 0.4V 2.7k to VCC on SDAIN, SCLIN, l –150 –250 –350 mV SDAOUT = SCLOUT = 0.4V, VCC = 5.5V VTHR SDAOUT, SCLOUT Logic Input Threshold Voltage VCC ≥ 2.9V 1.4 1.65 1.9 V VCC < 2.9V 1.1 1.35 1.6 V SDAIN, SCLIN Logic Input Threshold Voltage SDAIN, SCLIN Rising Edge, VCC = 2.3V, 5.5V 0.45 0.6 0.75 V VTHR(HYST) SDAOUT, SCLOUT Logic Input Threshold Voltage (Note 3) 50 mV Hysteresis SDAIN, SCLIN Logic Input Threshold Voltage (Note 3) 35 mV Hysteresis CIN Digital Input Capacitance SDAIN, SDAOUT, (Note 3) 10 pF SCLIN, SCLOUT ILEAK Input Leakage Current SDA, SCL Pins l ±5 μA VOL Output Low Voltage SDAOUT, SCLOUT Pins, ISINK = 4mA, l 0 400 mV SDAIN = SCLIN = 0V, VCC = 2.7V 2.7k to VCC on SDAOUT, SCLOUT, l 250 300 380 mV SDAIN = SCLIN = 0V VILMAX Buffer Input Logic Low Voltage SDAOUT, SCLOUT Pins l 1.2 V 4308f 3
The ELECTRICAL CHARACTERISTICS
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tIDLE Bus Idle Time l 55 95 175 μs VTHR_EN ENABLE Threshold Voltage ENABLE Rising Edge l 0.45 0.6 0.75 V VTHR_EN(HYST) ENABLE Threshold Voltage Hysteresis (Note 3) 35 mV IENABLE ENABLE Input Current ENABLE from 0V to VCC l 0.1 ±5 μA tPLH_EN ENABLE Delay Off-On (Figure 1) 95 μs tPHL_EN ENABLE Delay On-Off (Note 3), (Figure 1) 10 ns tPLH_READY READY Delay Off-On (Note 3), (Figure 1) 10 ns tPHL_READY READY Delay On-Off (Note 3), (Figure 1) 10 ns VOL_READY READY Output Low Voltage IREADY = 3mA, VCC = 2.3V l 0.4 V IOFF_READY READY Off Leakage Current VCC = READY = 5.5V l 0.1 ±5 μA
Prop Delay and Rise-Time Accelerators
tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 70 ns (Notes 2, 3), (Figure 1) tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 10 ns (Notes 2, 3), (Figure 1) tRISE SDA/SCL Transition Time Low to High CLOAD = 100pF, 10k to VCC on SDA, SCL, 30 300 ns (Notes 3, 4), (Figure 1) tFALL SDA/SCL Transition Time High to Low CLOAD = 100pF, 10k to VCC on SDA, SCL, 30 300 ns (Notes 3, 4), (Figure 1) IPULLUPAC Transient Boosted Pull-Up Current Positive Transition > 0.8V/μs on SDAOUT, 5 8 mA SCLOUT (Note 5)
Input-Output Connection
VOS Input to Output Offset Voltage (OUT – IN) 2.7k to VCC on SDAOUT, SCLOUT, l 250 300 380 mV SDAIN = SCLIN = 0.2V 2.7k to VCC on SDAOUT, SCLOUT, l 250 350 450 mV SDAIN = SCLIN = 0.4V, VCC = 5.5V Output to Input Offset Voltage (IN – OUT) 2.7k to VCC on SDAIN, SCLIN, l –150 –200 –300 mV SDAOUT = SCLOUT = 0.4V 2.7k to VCC on SDAIN, SCLIN, l –150 –250 –350 mV SDAOUT = SCLOUT = 0.4V, VCC = 5.5V VTHR SDAOUT, SCLOUT Logic Input Threshold Voltage VCC ≥ 2.9V 1.4 1.65 1.9 V VCC < 2.9V 1.1 1.35 1.6 V SDAIN, SCLIN Logic Input Threshold Voltage SDAIN, SCLIN Rising Edge, VCC = 2.3V, 5.5V 0.45 0.6 0.75 V VTHR(HYST) SDAOUT, SCLOUT Logic Input Threshold Voltage (Note 3) 50 mV Hysteresis SDAIN, SCLIN Logic Input Threshold Voltage (Note 3) 35 mV Hysteresis CIN Digital Input Capacitance SDAIN, SDAOUT, (Note 3) 10 pF SCLIN, SCLOUT ILEAK Input Leakage Current SDA, SCL Pins l ±5 μA VOL Output Low Voltage SDAOUT, SCLOUT Pins, ISINK = 4mA, l 0 400 mV SDAIN = SCLIN = 0V, VCC = 2.7V 2.7k to VCC on SDAOUT, SCLOUT, l 250 300 380 mV SDAIN = SCLIN = 0V VILMAX Buffer Input Logic Low Voltage SDAOUT, SCLOUT Pins l 1.2 V 4308f 3