Datasheet LTC4313-1, LTC4313-2, LTC4313-3 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 2-Wire Bus Buffers with High Noise Margin |
| 页数 / 页 | 20 / 9 — applicaTions inForMaTion. Input to Output Offset Voltage. Pull-Up … |
| 文件格式/大小 | PDF / 296 Kb |
| 文件语言 | 英语 |
applicaTions inForMaTion. Input to Output Offset Voltage. Pull-Up Resistor Value Selection
该数据表的模型线
- LTC4313CDD-1#PBF LTC4313CDD-1#TRPBF LTC4313CDD-2#PBF LTC4313CDD-2#TRPBF LTC4313CDD-3#PBF LTC4313CDD-3#TRPBF LTC4313CMS8-1#PBF LTC4313CMS8-1#TRPBF LTC4313CMS8-2#PBF LTC4313CMS8-2#TRPBF LTC4313CMS8-3#PBF LTC4313CMS8-3#TRPBF LTC4313IDD-1#PBF LTC4313IDD-1#TRPBF LTC4313IDD-2#PBF LTC4313IDD-2#TRPBF LTC4313IDD-3#PBF LTC4313IDD-3#TRPBF LTC4313IMS8-1#PBF LTC4313IMS8-1#TRPBF LTC4313IMS8-2#PBF LTC4313IMS8-2#TRPBF LTC4313IMS8-3#PBF LTC4313IMS8-3#TRPBF
- LTC4313CDD-1#PBF LTC4313CDD-1#TRPBF LTC4313CMS8-1#PBF LTC4313CMS8-1#TRPBF LTC4313IDD-1#PBF LTC4313IDD-1#TRPBF LTC4313IMS8-1#PBF LTC4313IMS8-1#TRPBF
文件文字版本
LTC4313-1/LTC4313-2/ LTC4313-3
applicaTions inForMaTion
of the LTC4313-1 and LTC4313-2 must be greater than
Input to Output Offset Voltage
or equal to 0.9•VCC. An example is shown in Figure 3 While propagating a logic low voltage on its SDA and SCL where the input bus voltage is greater than VCC. During a pins, the LTC4313 introduces a positive offset voltage rising edge, the input bus rise rate will be accelerated by between the input and output. When a logic low voltage the RTA up to a voltage of 2.97V after which the bus rise ≥200mV is driven on any of the LTC4313’s clock or data rate will reduce to a value that is determined by the bus pins, the LTC4313 regulates the voltage on the opposite current and bus capacitance. The RTA turn-off voltage is side to a slightly higher value. This is illustrated in Equa- less than the bus supply and the bus is not overdriven. tion 3, which uses SDA as an example:
Pull-Up Resistor Value Selection
V To guarantee that the RTAs are activated during a rising V DD,BUS SDAOUT = VSDAIN + 50mV + 15Ω • (3) edge, the bus must rise on its own with a positive slew rate RBUS of at least 0.4V/µs. To achieve this, choose a maximum R In Equation 3, VDD,BUS is the output bus supply voltage BUS using the formula: and RBUS is the SDAOUT bus pull-up resistance. (VDD,BUS(MIN) − VRTA(TH)) For driven logic low voltages < 200mV Equation 3 does RBUS ≤ V not apply as the saturation voltage of the open collector 0.4 • C (1) BUS output transistor results in a higher offset. For a driven input µs logic low voltage below 220mV, the output is guaranteed RBUS is the pull-up resistor, VDD,BUS(MIN) is the minimum to be below a V bus pull-up supply voltage, V OL of 400mV for bus pull-up currents up to RTA(TH) is the voltage at which 4mA. See the Typical Performance Characteristics section the RTA turns on and CBUS is the equivalent bus capaci- for offset variation as a function of the driven logic low tance. RBUS must also be large enough to guarantee that: voltage and bus pull-up current. (V ) R DD,BUS(MAX) − 0.4V (2) BUS ≥ 4mA This criterion ensures that the maximum bus current is less than 4mA. 5V 3.3V C1 V R1 R2 0.01µF CC R3 R4 R5 10k 10k 10k 10k 10k LTC4313-1 ENABLE READY READY SCL1 SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDA2 GND 4313123 F03
Figure 3. Level Shift Application Where the SDAIN and SCLIN Bus Pull-Up Supply Voltage Is Higher Than the Supply Voltage of the LTC4313
4313123f 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts
applicaTions inForMaTion
of the LTC4313-1 and LTC4313-2 must be greater than
Input to Output Offset Voltage
or equal to 0.9•VCC. An example is shown in Figure 3 While propagating a logic low voltage on its SDA and SCL where the input bus voltage is greater than VCC. During a pins, the LTC4313 introduces a positive offset voltage rising edge, the input bus rise rate will be accelerated by between the input and output. When a logic low voltage the RTA up to a voltage of 2.97V after which the bus rise ≥200mV is driven on any of the LTC4313’s clock or data rate will reduce to a value that is determined by the bus pins, the LTC4313 regulates the voltage on the opposite current and bus capacitance. The RTA turn-off voltage is side to a slightly higher value. This is illustrated in Equa- less than the bus supply and the bus is not overdriven. tion 3, which uses SDA as an example:
Pull-Up Resistor Value Selection
V To guarantee that the RTAs are activated during a rising V DD,BUS SDAOUT = VSDAIN + 50mV + 15Ω • (3) edge, the bus must rise on its own with a positive slew rate RBUS of at least 0.4V/µs. To achieve this, choose a maximum R In Equation 3, VDD,BUS is the output bus supply voltage BUS using the formula: and RBUS is the SDAOUT bus pull-up resistance. (VDD,BUS(MIN) − VRTA(TH)) For driven logic low voltages < 200mV Equation 3 does RBUS ≤ V not apply as the saturation voltage of the open collector 0.4 • C (1) BUS output transistor results in a higher offset. For a driven input µs logic low voltage below 220mV, the output is guaranteed RBUS is the pull-up resistor, VDD,BUS(MIN) is the minimum to be below a V bus pull-up supply voltage, V OL of 400mV for bus pull-up currents up to RTA(TH) is the voltage at which 4mA. See the Typical Performance Characteristics section the RTA turns on and CBUS is the equivalent bus capaci- for offset variation as a function of the driven logic low tance. RBUS must also be large enough to guarantee that: voltage and bus pull-up current. (V ) R DD,BUS(MAX) − 0.4V (2) BUS ≥ 4mA This criterion ensures that the maximum bus current is less than 4mA. 5V 3.3V C1 V R1 R2 0.01µF CC R3 R4 R5 10k 10k 10k 10k 10k LTC4313-1 ENABLE READY READY SCL1 SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDA2 GND 4313123 F03
Figure 3. Level Shift Application Where the SDAIN and SCLIN Bus Pull-Up Supply Voltage Is Higher Than the Supply Voltage of the LTC4313
4313123f 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts