Datasheet LTC4315 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 2-Wire Bus Buffer with High Noise Margin |
| 页数 / 页 | 20 / 1 — FEATURES. DESCRIPTION. Bidirectional Buffer Increases Fanout. High Noise … |
| 文件格式/大小 | PDF / 282 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTION. Bidirectional Buffer Increases Fanout. High Noise Margin with VIL = 0.3 • VCC
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LTC4315 2-Wire Bus Buffer with High Noise Margin
FEATURES DESCRIPTION
n
Bidirectional Buffer Increases Fanout
The LTC4315 is a hot-swappable 2-wire bus buffer n
High Noise Margin with VIL = 0.3 • VCC
that provides bidirectional buffering, while maintain- n
Compatible with Non-Compliant I2C Devices That
ing a low offset voltage and high noise margin up to
Drive a High VOL
0.3 • VCC. The high noise margin allows the LTC4315 to be n
Selectable Rise Time Accelerator Current
interoperable with devices that drive a high VOL (>0.4V) n
Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses
and allows multiple LTC4315s to be cascaded. The LTC4315 n Prevents SDA and SCL Corruption During Live Board supports level translation between 1.5V, 1.8V, 2.5V, 3.3V Insertion and Removal from Backplane and 5V busses. n Stuck Bus Disconnect and Recovery During insertion, the SDA and SCL lines are precharged to n Compatible with I2C, I2C Fast Mode and SMBus 1V to minimize bus disturbances. Connection is established n ±4kV Human Body Model ESD Ruggedness between the input and output after ENABLE is asserted n High Impedance SDA, SCL pins When Unpowered high and a stop bit or bus idle condition has been detected n 12-Lead (4mm × 3mm) DFN and 12-Lead MSOP on the SDA and SCL pins. Packages If both data and clock are not simultaneously high at least once in 45ms and DISCEN is high, a FAULT signal
APPLICATIONS
is generated indicating a stuck bus low condition and the n Capacitance Buffers/Bus Extender input is disconnected from the output. Up to 16 clock n Live Board Insertion pulses are subsequently generated to free the stuck bus. n Telecommunications Systems Including ATCA A three state ACC pin enables input and output side rise n Level Translation time accelerators of various strengths. n PMBus L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their n Servers respective owners. Protected by U.S. patents, including 6356140, 6650174, 7032051, 7478286.
TYPICAL APPLICATION 400kHz Operation
3.3V 5V RBUS_IN = 2.7kΩ, CBUS_IN = 50pF RBUS_OUT = 1.3kΩ, CBUS_OUT = 400pF, ACC = 0V 0.01μF 2.7k 2.7k VCC VCC2 10k 1.3k 1.3k 10k SCLOUT DISCEN /DIV ENABLE 1V SCLIN LTC4315 READY READY SCL1 SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDA2 500ns/DIV 4315 TA01b ACC FAULT FAULT GND 4315 TA01a 4315f 1 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS
FEATURES DESCRIPTION
n
Bidirectional Buffer Increases Fanout
The LTC4315 is a hot-swappable 2-wire bus buffer n
High Noise Margin with VIL = 0.3 • VCC
that provides bidirectional buffering, while maintain- n
Compatible with Non-Compliant I2C Devices That
ing a low offset voltage and high noise margin up to
Drive a High VOL
0.3 • VCC. The high noise margin allows the LTC4315 to be n
Selectable Rise Time Accelerator Current
interoperable with devices that drive a high VOL (>0.4V) n
Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses
and allows multiple LTC4315s to be cascaded. The LTC4315 n Prevents SDA and SCL Corruption During Live Board supports level translation between 1.5V, 1.8V, 2.5V, 3.3V Insertion and Removal from Backplane and 5V busses. n Stuck Bus Disconnect and Recovery During insertion, the SDA and SCL lines are precharged to n Compatible with I2C, I2C Fast Mode and SMBus 1V to minimize bus disturbances. Connection is established n ±4kV Human Body Model ESD Ruggedness between the input and output after ENABLE is asserted n High Impedance SDA, SCL pins When Unpowered high and a stop bit or bus idle condition has been detected n 12-Lead (4mm × 3mm) DFN and 12-Lead MSOP on the SDA and SCL pins. Packages If both data and clock are not simultaneously high at least once in 45ms and DISCEN is high, a FAULT signal
APPLICATIONS
is generated indicating a stuck bus low condition and the n Capacitance Buffers/Bus Extender input is disconnected from the output. Up to 16 clock n Live Board Insertion pulses are subsequently generated to free the stuck bus. n Telecommunications Systems Including ATCA A three state ACC pin enables input and output side rise n Level Translation time accelerators of various strengths. n PMBus L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their n Servers respective owners. Protected by U.S. patents, including 6356140, 6650174, 7032051, 7478286.
TYPICAL APPLICATION 400kHz Operation
3.3V 5V RBUS_IN = 2.7kΩ, CBUS_IN = 50pF RBUS_OUT = 1.3kΩ, CBUS_OUT = 400pF, ACC = 0V 0.01μF 2.7k 2.7k VCC VCC2 10k 1.3k 1.3k 10k SCLOUT DISCEN /DIV ENABLE 1V SCLIN LTC4315 READY READY SCL1 SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDA2 500ns/DIV 4315 TA01b ACC FAULT FAULT GND 4315 TA01a 4315f 1 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS