Datasheet LTC5531 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Precision 300MHz to 7GHz RF Detector with Shutdown and Offset Adjustment |
| 页数 / 页 | 12 / 8 — PI FU CTIO S. RFIN (Pin 1):. OS (Pin 4):. GND (Pin 2):. SHDN (Pin 3):. … |
| 文件格式/大小 | PDF / 226 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. RFIN (Pin 1):. OS (Pin 4):. GND (Pin 2):. SHDN (Pin 3):. VOUT (Pin 5):. CC (Pin 6):. BLOCK DIAGRA
该数据表的模型线
文件文字版本
LTC5531
U U U PI FU CTIO S RFIN (Pin 1):
RF Input Voltage. Referenced to VCC. A applied. In shutdown VOUT is connected to ground via a coupling capacitor must be used to connect to the RF 280Ω resistor. signal source. The frequency range is 300MHz to 7GHz.
V
This pin has an internal 500Ω termination, an internal
OS (Pin 4):
VOUT Offset Voltage Adjustment. This pin adjusts the starting V Schottky diode detector and a peak detector capacitor. OUT voltage when no RF signal is present. For VOS from 0V to 120mV, VOUT is unaffected by
GND (Pin 2):
Ground. VOS. For VOS > 120mV, VOUT is the sum of VOS plus the
SHDN (Pin 3):
Shutdown Input. A logic low on the SHDN detected RF signal. pin places the part in shutdown mode. A logic high enables
VOUT (Pin 5):
Detector Output. the part. SHDN has an internal 160k pulldown resistor to
V
ensure that the part is in shutdown when no input is
CC (Pin 6):
Power Supply Voltage, 2.7V to 6V. VCC should be bypassed appropriately with ceramic capacitors.
W BLOCK DIAGRA
RFSOURCE VCC 6 SD + BUFFER 5 VOUT BIAS SHUTDOWN – 500Ω 1 30k RFIN 500Ω 30k 180Ω SD 100Ω 31k 25pF + RF DET + 4 VOS 24k 80k – SD – 50µA 50µA 80k 120mV GND 2 160k + 5531 BD 3 SHDN 5531f 8
U U U PI FU CTIO S RFIN (Pin 1):
RF Input Voltage. Referenced to VCC. A applied. In shutdown VOUT is connected to ground via a coupling capacitor must be used to connect to the RF 280Ω resistor. signal source. The frequency range is 300MHz to 7GHz.
V
This pin has an internal 500Ω termination, an internal
OS (Pin 4):
VOUT Offset Voltage Adjustment. This pin adjusts the starting V Schottky diode detector and a peak detector capacitor. OUT voltage when no RF signal is present. For VOS from 0V to 120mV, VOUT is unaffected by
GND (Pin 2):
Ground. VOS. For VOS > 120mV, VOUT is the sum of VOS plus the
SHDN (Pin 3):
Shutdown Input. A logic low on the SHDN detected RF signal. pin places the part in shutdown mode. A logic high enables
VOUT (Pin 5):
Detector Output. the part. SHDN has an internal 160k pulldown resistor to
V
ensure that the part is in shutdown when no input is
CC (Pin 6):
Power Supply Voltage, 2.7V to 6V. VCC should be bypassed appropriately with ceramic capacitors.
W BLOCK DIAGRA
RFSOURCE VCC 6 SD + BUFFER 5 VOUT BIAS SHUTDOWN – 500Ω 1 30k RFIN 500Ω 30k 180Ω SD 100Ω 31k 25pF + RF DET + 4 VOS 24k 80k – SD – 50µA 50µA 80k 120mV GND 2 160k + 5531 BD 3 SHDN 5531f 8