Datasheet LTC5533 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 300MHz to 11GHz Precision Dual RF Power Detector |
| 页数 / 页 | 12 / 8 — PI FU CTIO S. VCC1, VCC2 (Pins 1, 4):. VOUT1, VOUT2 (Pins 2, 5):. GND1, … |
| 文件格式/大小 | PDF / 252 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. VCC1, VCC2 (Pins 1, 4):. VOUT1, VOUT2 (Pins 2, 5):. GND1, GND2 (Pins 11, 8):. VOS1, VOS2 (Pins 3, 6):
该数据表的模型线
文件文字版本
LTC5533
U U U PI FU CTIO S VCC1, VCC2 (Pins 1, 4):
Power Supply Voltage, 2.7V to 6V. has an internal 160k pulldown resistor to ensure that the VCC should be bypassed appropriately with ceramic detector is shutdown when no SHDN input is applied. In capacitors. shutdown VOUT is connected to ground via a 280Ω resis- tor. Channels can be shut down independently.
VOUT1, VOUT2 (Pins 2, 5):
Detector Outputs.
GND1, GND2 (Pins 11, 8):
Ground.
VOS1, VOS2 (Pins 3, 6):
VOUT Offset Voltage Adjustments. These pins adjust the starting VOUT voltage when no RF
RFIN1, RFIN2 (Pins 12, 9):
RF Input Voltage. Referenced signal is present. For VOS from 0V to 130mV, VOUT is to VCC. A coupling capacitor must be used to connect to unaffected by VOS. For VOS > 130mV, VOUT is the sum of the RF signal source. These pins have internal 500Ω VOS plus the detected RF signal. terminations, Schottky diode detectors and peak detector capacitors.
SHDN1, SHDN2 (Pin 10, 7):
Shutdown Inputs. A logic low on the SHDN pin places the corresponding detector in
Exposed Pad (Pin13):
Ground. shutdown mode. A logic high enables the detector. SHDN
W BLOCK DIAGRA (One Channel)
RFSOURCE 12pF TO 200pF (DEPENDING ON APPLICATION) VCC ONE CHANNEL SD + BUFFER VOUT BIAS SD – 500Ω 30k RFIN 500Ω 30k 180Ω SD 100Ω 31k 25pF + RF DET + VOS 24k 80k – SD – 80k 50µA 50µA 120mV GND 160k + 5531 BD SHDN 5533f 8
U U U PI FU CTIO S VCC1, VCC2 (Pins 1, 4):
Power Supply Voltage, 2.7V to 6V. has an internal 160k pulldown resistor to ensure that the VCC should be bypassed appropriately with ceramic detector is shutdown when no SHDN input is applied. In capacitors. shutdown VOUT is connected to ground via a 280Ω resis- tor. Channels can be shut down independently.
VOUT1, VOUT2 (Pins 2, 5):
Detector Outputs.
GND1, GND2 (Pins 11, 8):
Ground.
VOS1, VOS2 (Pins 3, 6):
VOUT Offset Voltage Adjustments. These pins adjust the starting VOUT voltage when no RF
RFIN1, RFIN2 (Pins 12, 9):
RF Input Voltage. Referenced signal is present. For VOS from 0V to 130mV, VOUT is to VCC. A coupling capacitor must be used to connect to unaffected by VOS. For VOS > 130mV, VOUT is the sum of the RF signal source. These pins have internal 500Ω VOS plus the detected RF signal. terminations, Schottky diode detectors and peak detector capacitors.
SHDN1, SHDN2 (Pin 10, 7):
Shutdown Inputs. A logic low on the SHDN pin places the corresponding detector in
Exposed Pad (Pin13):
Ground. shutdown mode. A logic high enables the detector. SHDN
W BLOCK DIAGRA (One Channel)
RFSOURCE 12pF TO 200pF (DEPENDING ON APPLICATION) VCC ONE CHANNEL SD + BUFFER VOUT BIAS SD – 500Ω 30k RFIN 500Ω 30k 180Ω SD 100Ω 31k 25pF + RF DET + VOS 24k 80k – SD – 80k 50µA 50µA 120mV GND 160k + 5531 BD SHDN 5533f 8