Datasheet LTC5587 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 6 GHz RMS Power Detector with Digital Output |
| 页数 / 页 | 20 / 10 — PIN FUNCTIONS. SDO (Pin 1):. VCC (Pin 8):. SCK (Pin 2):. EN (Pin 9):. … |
| 文件格式/大小 | PDF / 325 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. SDO (Pin 1):. VCC (Pin 8):. SCK (Pin 2):. EN (Pin 9):. OVDD (Pin 3):. VREF (Pin 10):. VOUT (Pin 4):. VDD (Pin 11):
该数据表的模型线
文件文字版本
LTC5587
PIN FUNCTIONS SDO (Pin 1):
Three-State Serial Data Output. The A/D
VCC (Pin 8):
Detector Power Supply Voltage, 2.7V to 3.6V. conversion result is shifted out on SDO as a serial data Can be connected to the VDD voltage supply. VCC should stream with MSB first. The data stream consists of 12 bits be bypassed with a 1μF ceramic capacitor. If VCC and VDD of conversion data followed by trailing zeros. are tied together, then bypass with 2.2μF.
SCK (Pin 2):
Shift Clock Input. The SCK serial clock syn-
EN (Pin 9):
Detector Enable. A logic low or no-connect chronizes the serial data transfer. SDO data transitions on the enable pin shuts down the detector. A logic high on the falling edge of SCK. enables the detector. An internal 500k pull-down resistor ensures the detector is off when the pin is left floating.
OVDD (Pin 3):
ADC Output Driver Supply Voltage, 1.0V to 3.6V. OVDD should be bypassed with a 1μF ceramic
VREF (Pin 10):
ADC Reference Input Voltage. VREF defines capacitor. OVDD can be driven separately from VDD and the input span of the ADC, 0V to VREF. The VREF range OVDD can be higher than VDD. is 1.4V to VDD. Bypass to ground with a 1μF ceramic capacitor.
VOUT (Pin 4):
Detector Analog Voltage Output. An internal series 300Ω resistor at the detector output allows for
VDD (Pin 11):
ADC Power Supply Voltage, 2.7V to 3.6V. simple R-C filtering with a capacitor placed on this pin to VDD should be bypassed with a 1μF ceramic capacitor. GND. A 1000pF capacitor is recommended for a corner
CONV (Pin 12):
Convert Input. This active high signal starts frequency of 500kHz. a conversion on the rising edge. The ADC automatically
CSQ (Pin 6):
Optional low-frequency range extension powers down after conversion. A logic low on this input capacitor for frequencies below 250MHz. Connect 0.01μF enables the SDO pin, allowing the data to be shifted out. from this pin to ground for 10MHz operation.
GND (Pin 5, Exposed Pad Pin 13):
Ground. For high-
RF (Pin 7):
RF Input Voltage. Should be externally frequency operation, backside ground connection should DC-blocked. A capacitor of 1000pF is recommended. This have a low-inductance connection to the pcb ground using pin has an internal 205Ω termination. many through-hole vias. See layout information.
BLOCK DIAGRAM
13 4 11 3 EXPOSED VOUT VDD OVDD PAD OUTPUT BUFFER 150kHz LPF RF 300Ω RMS 7 THREE-STATE SDO DETECTOR S/H 12-BIT ADC SERIAL OUTPUT 1 PORT SCK 2 BIAS TIMING CONV LOGIC 12 C EN V GND V SQ CC REF 6 9 8 5 10 5587 BD 5587f 10 Document Outline FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM TIMING DIAGRAMS TEST CIRCUIT APPLICATIONS INFORMATION PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS
PIN FUNCTIONS SDO (Pin 1):
Three-State Serial Data Output. The A/D
VCC (Pin 8):
Detector Power Supply Voltage, 2.7V to 3.6V. conversion result is shifted out on SDO as a serial data Can be connected to the VDD voltage supply. VCC should stream with MSB first. The data stream consists of 12 bits be bypassed with a 1μF ceramic capacitor. If VCC and VDD of conversion data followed by trailing zeros. are tied together, then bypass with 2.2μF.
SCK (Pin 2):
Shift Clock Input. The SCK serial clock syn-
EN (Pin 9):
Detector Enable. A logic low or no-connect chronizes the serial data transfer. SDO data transitions on the enable pin shuts down the detector. A logic high on the falling edge of SCK. enables the detector. An internal 500k pull-down resistor ensures the detector is off when the pin is left floating.
OVDD (Pin 3):
ADC Output Driver Supply Voltage, 1.0V to 3.6V. OVDD should be bypassed with a 1μF ceramic
VREF (Pin 10):
ADC Reference Input Voltage. VREF defines capacitor. OVDD can be driven separately from VDD and the input span of the ADC, 0V to VREF. The VREF range OVDD can be higher than VDD. is 1.4V to VDD. Bypass to ground with a 1μF ceramic capacitor.
VOUT (Pin 4):
Detector Analog Voltage Output. An internal series 300Ω resistor at the detector output allows for
VDD (Pin 11):
ADC Power Supply Voltage, 2.7V to 3.6V. simple R-C filtering with a capacitor placed on this pin to VDD should be bypassed with a 1μF ceramic capacitor. GND. A 1000pF capacitor is recommended for a corner
CONV (Pin 12):
Convert Input. This active high signal starts frequency of 500kHz. a conversion on the rising edge. The ADC automatically
CSQ (Pin 6):
Optional low-frequency range extension powers down after conversion. A logic low on this input capacitor for frequencies below 250MHz. Connect 0.01μF enables the SDO pin, allowing the data to be shifted out. from this pin to ground for 10MHz operation.
GND (Pin 5, Exposed Pad Pin 13):
Ground. For high-
RF (Pin 7):
RF Input Voltage. Should be externally frequency operation, backside ground connection should DC-blocked. A capacitor of 1000pF is recommended. This have a low-inductance connection to the pcb ground using pin has an internal 205Ω termination. many through-hole vias. See layout information.
BLOCK DIAGRAM
13 4 11 3 EXPOSED VOUT VDD OVDD PAD OUTPUT BUFFER 150kHz LPF RF 300Ω RMS 7 THREE-STATE SDO DETECTOR S/H 12-BIT ADC SERIAL OUTPUT 1 PORT SCK 2 BIAS TIMING CONV LOGIC 12 C EN V GND V SQ CC REF 6 9 8 5 10 5587 BD 5587f 10 Document Outline FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM TIMING DIAGRAMS TEST CIRCUIT APPLICATIONS INFORMATION PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS