Datasheet ICL7106, ICL7107, ICL7107S (Intersil) - 6

link to page 6 link to page 10 link to page 10 ICL7106, ICL7107, ICL7107S Detailed Description to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading Analog Section displayed is: Figure 3 shows the analog section for the ICL7106 and ICL7107.  V  DISPLAY COUNT = 1000 IN -------- (EQ. 1) Each measurement cycle is divided into three phases. They are V  REF (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) deintegrate (DE). Differential Input Auto-Zero Phase The input can accept differential voltages anywhere within the During auto-zero three things happen. First, input high and low are common mode range of the input amplifier, or specifically from disconnected from the pins and internally shorted to analog 0.5V below the positive supply to 1V above the negative supply. In COMMON. Second, the reference capacitor is charged to the this range, the system has a CMRR of 86dB typical. However, care reference voltage. Third, a feedback loop is closed around the must be exercised to assure the integrator output does not system to charge the auto-zero capacitor C saturate. A worst case condition would be a large positive common AZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. mode voltage with a near full scale negative differential input Since the comparator is included in the loop, the A-Z accuracy is voltage. The negative input signal drives the integrator positive limited only by the noise of the system. In any case, the offset when most of its swing has been used up by the positive common referred to the input is less than 10µV. mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale Signal Integrate Phase swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected Differential Reference to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential The reference voltage can be generated anywhere within the power voltage can be within a wide common mode range: up to 1V from supply voltage of the converter. The main source of common mode either supply. If, on the other hand, the input signal has no return error is a roll-over voltage caused by the reference capacitor losing or with respect to the converter power supply, IN LO can be tied to gaining charge to stray capacity on its nodes. If there is a large analog COMMON to establish the correct common mode voltage. At common mode voltage, the reference capacitor can gain charge the end of this phase, the polarity of the integrated signal is (increase voltage) when called up to deintegrate a positive signal but determined. lose charge (decrease voltage) when called up to deintegrate a negative input signal. This difference in reference for positive or Deintegrate Phase negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in The final phase is deintegrate, or reference integrate. Input low is comparison to the stray capacitance, this error can be held to less internally connected to analog COMMON and input high is than 0.5 count worst case. (see “Component Value Selection” on connected across the previously charged reference capacitor. page 10.) Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output
STRAY C STRAY REF RINT C C AZ INT C REF HI REF LO REF+ CREF- BUFFER V+ A-Z INT 34 36 35 33 28 1 29 27 V+ INTEGRATOR A-Z A-Z 10
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A - TO - - + DIGITAL + + 31 SECTION 2.8V IN HI INT DE- DE+ INPUT 6.2V A-Z HIGH A-Z COMPARATOR N -+ DE+ DE- 32 COMMON INT A-Z AND DE(±) INPUT 30 LOW IN LO V-
FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107 FN3082 Rev 9.00 Page 6 of 17 October 24, 2014