Datasheet ADXL372 (Analog Devices) - 8

Data Sheet ADXL372 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C ND S G NI V 16 15 14 VDDI/O 1 13 GND NIC 2 12 GND ADXL372 RESERVED 3 11 INT1 TOP VIEW (Not to Scale) SCLK 4 10 RESERVED RESERVED 5 9 INT2 6 7 8 A SO CL SD/ S MI / SI CS MO NOTES
003
1. NIC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED.
15430- Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VDDI/O Supply Voltage for Digital Input/Output. 2 NIC No Connect. This pin is not internally connected. 3 RESERVED Reserved. This pin may be left unconnected or connected to GND. 4 SCLK SPI Serial Communications Clock. 5 RESERVED Reserved. This pin may be left unconnected or connected to GND. 6 MOSI/SDA SPI Master Output, Slave Input (MOSI). I2C Serial Data (SDA). 7 MISO SPI Master Input, Slave Output. 8 CS/SCL SPI Chip Select (CS). I2C Serial Communications Clock (SCL). 9 INT2 Interrupt 2 Output. This pin also serves as an input for synchronized sampling. 10 RESERVED Reserved. This pin may be left unconnected or connected to GND. 11 INT1 Interrupt 1 Output. This pin also serves as an input for external clocking. 12 GND Ground. This pin must be connected to ground. 13 GND Ground. This pin must be connected to ground. 14 VS Supply Voltage. 15 NIC No Connect. This pin is not internally connected. 16 GND Ground. This pin must be connected to ground. Rev. 0 | Page 7 of 56 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE RECOMMENDED SOLDERING PROFILE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION MECHANICAL DEVICE OPERATION OPERATING MODES Measurement Mode Instant On Mode Wake-Up Mode Standby BANDWIDTH Low-Pass Antialiasing Filter High-Pass Filter Filter Settling Time Selectable ODR POWER/NOISE TRADE-OFF POWER SAVINGS AUTONOMOUS EVENT DETECTION ACTIVITY AND INACTIVITY Low-Pass Activity Detect Filter Activity Detection Referenced and Absolute Configurations Activity Timer Activity Detection in Wake-Up Mode Inactivity Detection Referenced and Absolute Configurations Inactivity Timer Linking Activity and Inactivity Detection Default Mode Linked Mode Loop Mode Autosleep Using the AWAKE Bit MOTION WARNING IMPACT DETECTION FEATURES WIDE BANDWIDTH INSTANT ON IMPACT DETECTION CAPTURING IMPACT EVENTS FIFO BENEFITS OF THE FIFO System Level Power Savings Data Recording/Event Context USING THE FIFO FIFO Disabled Oldest Saved Mode (First N) Stream Mode (Last N) Triggered Mode RETRIEVING DATA FROM FIFO INTERRUPTS INTERRUPT PINS Alternate Functions TYPES OF INTERRUPTS Activity and Inactivity Interrupts Data Ready Interrupt FIFO Interrupts FIFO Watermark FIFO Ready Overrun ADDITIONAL FEATURES USING AN EXTERNAL CLOCK SYNCHRONIZED DATA SAMPLING SELF TEST Self Test Procedure USER REGISTER PROTECTION USER OFFSET TRIMS SERIAL COMMUNICATIONS SERIAL INTERFACE SPI Protocol I2C Protocol MULTIBYTE TRANSFERS INVALID ADDRESSES AND ADDRESS FOLDING SPI Timing Diagrams I2C Timing Diagrams REGISTER MAP REGISTER DETAILS ANALOG DEVICES ID REGISTER ANALOG DEVICES MEMS ID REGISTER DEVICE ID REGISTER PRODUCT REVISION ID REGISTER STATUS REGISTER ACTIVITY STATUS REGISTER FIFO ENTRIES REGISTER, MSB FIFO ENTRIES REGISTER, LSB X-AXIS DATA REGISTER, MSB X-AXIS DATA REGISTER, LSB Y-AXIS DATA REGISTER, MSB Y-AXIS DATA REGISTER, LSB Z-AXIS DATA REGISTER, MSB Z-AXIS DATA REGISTER, LSB HIGHEST PEAK DATA REGISTERS X-AXIS HIGHEST PEAK DATA REGISTER, MSB X-AXIS HIGHEST PEAK DATA REGISTER, LSB Y-AXIS HIGHEST PEAK DATA REGISTER, MSB Y-AXIS HIGHEST PEAK DATA REGISTER, LSB Z-AXIS HIGHEST PEAK DATA REGISTER, MSB Z-AXIS HIGHEST PEAK DATA REGISTER, LSB OFFSET TRIM REGISTERS X-AXIS OFFSET TRIM REGISTER, LSB Y-AXIS OFFSET TRIM REGISTER, LSB Z-AXIS OFFSET TRIM REGISTER, LSB X-AXIS ACTIVITY THRESHOLD REGISTER, MSB X-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB Y-AXIS ACTIVITY THRESHOLD REGISTER, MSB Y-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB Z-AXIS ACTIVITY THRESHOLD REGISTER, MSB Z-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB ACTIVITY TIME REGISTER X-AXIS INACTIVITY THRESHOLD REGISTER, MSB X-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB Y-AXIS INACTIVITY THRESHOLD REGISTER, MSB Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB Z-AXIS INACTIVITY THRESHOLD REGISTER, MSB Z-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB INACTIVITY TIME REGISTERS INACTIVITY TIMER REGISTER, MSB INACTIVITY TIMER REGISTER, LSB X-AXIS MOTION WARNING THRESHOLD REGISTER, MSB X-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB Y-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB Y-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB Z-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB HIGH-PASS FILTER SETTINGS REGISTER FIFO SAMPLES REGISTER FIFO CONTROL REGISTER INTERRUPT PIN FUNCTION MAP REGISTERS INT2 FUNCTION MAP REGISTER EXTERNAL TIMING CONTROL REGISTER MEASUREMENT CONTROL REGISTER POWER CONTROL REGISTER SELF TEST REGISTER RESET (CLEARS) REGISTER, PART IN STANDBY MODE FIFO ACCESS REGISTER APPLICATIONS INFORMATION APPLICATION EXAMPLES Power Supply Decoupling Using External Timing Triggers OPERATION AT VOLTAGES OTHER THAN 2.5 V OPERATION AT TEMPERATURES OTHER THAN AMBIENT MECHANICAL CONSIDERATIONS FOR MOUNTING AXES OF ACCELERATION SENSITIVITY LAYOUT AND DESIGN RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE