Datasheet ADXL354, ADXL355 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Low Noise, Low Drift, Low Power 3-Axis Accelerometer with digital output |
| 页数 / 页 | 42 / 2 — ADXL354/ADXL355. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
ADXL354/ADXL355. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 9/2016—Revision 0: Initial Version
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ADXL354/ADXL355 Data Sheet TABLE OF CONTENTS
Features .. 1 NVM_BUSY ... 28 Applications ... 1 External Synchronization and Interpolation .. 29 Functional Block Diagrams ... 1 ADXL355 Register Map ... 31 General Description ... 1 Register Definitions.. 32 Revision History ... 2 Analog Devices ID Register .. 32 Specifications ... 3 Analog Devices MEMS ID Register ... 32 Analog Output for the ADXL354 ... 3 Device ID Register ... 32 Digital Output for the ADXL355 ... 4 Product Revision ID Register ... 32 SPI Digital Interface Characteristics for the ADXL355 .. 5 Status Register ... 32 I2C Digital Interface Characteristics for the ADXL355 ... 6 FIFO Entries Register .. 33 Absolute Maximum Ratings .. 8 Temperature Data Registers .. 33 Thermal Resistance .. 8 X-Axis Data Registers .. 33 ESD Caution .. 8 Y-Axis Data Registers .. 34 Pin Configurations and Function Descriptions ... 9 Z-Axis Data Registers .. 34 Typical Performance Characteristics ... 11 FIFO Access Register ... 35 Root Allan Variance (RAV) ADXL355 Characteristics ... 19 X-Axis Offset Trim Registers .. 35 Theory of Operation .. 20 Y-Axis Offset Trim Registers .. 35 Analog Output .. 20 Z-Axis Offset Trim Registers .. 36 Digital Output ... 21 Activity Enable Register .. 36 Axes of Acceleration Sensitivity ... 21 Activity Threshold Registers ... 36 Power Sequencing .. 22 Activity Count Register ... 36 Power Supply Description ... 22 Filter Settings Register ... 37 Overrange Protection ... 22 FIFO Samples Register .. 37 Self Test .. 22 Interrupt Pin (INTx) Function Map Register... 37 Filter ... 23 Data Synchronization .. 38 Serial Communications ... 25 I2C Speed, Interrupt Polarity, and Range Register ... 38 SPI Protocol ... 25 Power Control Register ... 38 I2C Protocol ... 26 Self Test Register ... 39 Reading Acceleration or Temperature Data from the Interface Reset Register .. 39 ... 26 Recommended Soldering Profile ... 40 FIFO ... 27 PCB Footprint Pattern ... 41 Interrupts ... 28 Packaging and Ordering Information ... 42 DATA_RDY ... 28 Outline Dimensions ... 42 DRDY Pin .. 28 Branding Information .. 42 FIFO_FULL ... 28 Ordering Guide .. 42 FIFO_OVR .. 28 Activity ... 28
REVISION HISTORY 9/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 42 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ANALOG OUTPUT FOR THE ADXL354 DIGITAL OUTPUT FOR THE ADXL355 SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355 I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ROOT ALLAN VARIANCE (RAV) ADXL355 CHARACTERISTICS THEORY OF OPERATION ANALOG OUTPUT DIGITAL OUTPUT AXES OF ACCELERATION SENSITIVITY POWER SEQUENCING POWER SUPPLY DESCRIPTION VSUPPLY V1P8ANA V1P8DIG VDDIO OVERRANGE PROTECTION SELF TEST FILTER SERIAL COMMUNICATIONS SPI PROTOCOL I2C PROTOCOL READING ACCELERATION OR TEMPERATURE DATA FROM THE INTERFACE FIFO INTERRUPTS DATA_RDY DRDY PIN FIFO_FULL FIFO_OVR ACTIVITY NVM_BUSY EXTERNAL SYNCHRONIZATION AND INTERPOLATION EXT_SYNC = 00—No External Sync or Interpolation EXT_SYNC = 10—External Sync with Interpolation EXT_SYNC = 01—External Sync and External Clock ADXL355 REGISTER MAP REGISTER DEFINITIONS ANALOG DEVICES ID REGISTER Address: 0x00, Reset: 0xAD, Name: DEVID_AD ANALOG DEVICES MEMS ID REGISTER Address: 0x01, Reset: 0x1D, Name: DEVID_MST DEVICE ID REGISTER Address: 0x02, Reset: 0xED, Name: PARTID PRODUCT REVISION ID REGISTER Address: 0x03, Reset: 0x00, Name: REVID STATUS REGISTER Address: 0x04, Reset: 0x00, Name: STATUS FIFO ENTRIES REGISTER Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES TEMPERATURE DATA REGISTERS Address: 0x06, Reset: 0x00, Name: TEMP2 Address: 0x07, Reset: 0x00, Name: TEMP1 X-AXIS DATA REGISTERS Address: 0x08, Reset: 0x00, Name: XDATA3 Address: 0x09, Reset: 0x00, Name: XDATA2 Address: 0x0A, Reset: 0x00, Name: XDATA1 Y-AXIS DATA REGISTERS Address: 0x0B, Reset: 0x00, Name: YDATA3 Address: 0x0C, Reset: 0x00, Name: YDATA2 Address: 0x0D, Reset: 0x00, Name: YDATA1 Z-AXIS DATA REGISTERS Address: 0x0E, Reset: 0x00, Name: ZDATA3 Address: 0x0F, Reset: 0x00, Name: ZDATA2 Address: 0x10, Reset: 0x00, Name: ZDATA1 FIFO ACCESS REGISTER Address: 0x11, Reset: 0x00, Name: FIFO_DATA X-AXIS OFFSET TRIM REGISTERS Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L Y-AXIS OFFSET TRIM REGISTERS Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L Z-AXIS OFFSET TRIM REGISTERS Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L ACTIVITY ENABLE REGISTER Address: 0x24, Reset: 0x00, Name: ACT_EN ACTIVITY THRESHOLD REGISTERS Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L ACTIVITY COUNT REGISTER Address: 0x27, Reset: 0x01, Name: ACT_COUNT FILTER SETTINGS REGISTER Address: 0x28, Reset: 0x00, Name: Filter FIFO SAMPLES REGISTER Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES INTERRUPT PIN (INTx) FUNCTION MAP REGISTER Address: 0x2A, Reset: 0x00, Name: INT_MAP DATA SYNCHRONIZATION Address: 0x2B, Reset: 0x00, Name: Sync I2C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER Address: 0x2C, Reset: 0x81, Name: Range POWER CONTROL REGISTER Address: 0x2D, Reset: 0x01, Name: POWER_CTL SELF TEST REGISTER Address: 0x2E, Reset: 0x00, Name: SELF_TEST RESET REGISTER Address: 0x2F, Reset: 0x00, Name: Reset RECOMMENDED SOLDERING PROFILE PCB FOOTPRINT PATTERN PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS BRANDING INFORMATION ORDERING GUIDE
ADXL354/ADXL355 Data Sheet TABLE OF CONTENTS
Features .. 1 NVM_BUSY ... 28 Applications ... 1 External Synchronization and Interpolation .. 29 Functional Block Diagrams ... 1 ADXL355 Register Map ... 31 General Description ... 1 Register Definitions.. 32 Revision History ... 2 Analog Devices ID Register .. 32 Specifications ... 3 Analog Devices MEMS ID Register ... 32 Analog Output for the ADXL354 ... 3 Device ID Register ... 32 Digital Output for the ADXL355 ... 4 Product Revision ID Register ... 32 SPI Digital Interface Characteristics for the ADXL355 .. 5 Status Register ... 32 I2C Digital Interface Characteristics for the ADXL355 ... 6 FIFO Entries Register .. 33 Absolute Maximum Ratings .. 8 Temperature Data Registers .. 33 Thermal Resistance .. 8 X-Axis Data Registers .. 33 ESD Caution .. 8 Y-Axis Data Registers .. 34 Pin Configurations and Function Descriptions ... 9 Z-Axis Data Registers .. 34 Typical Performance Characteristics ... 11 FIFO Access Register ... 35 Root Allan Variance (RAV) ADXL355 Characteristics ... 19 X-Axis Offset Trim Registers .. 35 Theory of Operation .. 20 Y-Axis Offset Trim Registers .. 35 Analog Output .. 20 Z-Axis Offset Trim Registers .. 36 Digital Output ... 21 Activity Enable Register .. 36 Axes of Acceleration Sensitivity ... 21 Activity Threshold Registers ... 36 Power Sequencing .. 22 Activity Count Register ... 36 Power Supply Description ... 22 Filter Settings Register ... 37 Overrange Protection ... 22 FIFO Samples Register .. 37 Self Test .. 22 Interrupt Pin (INTx) Function Map Register... 37 Filter ... 23 Data Synchronization .. 38 Serial Communications ... 25 I2C Speed, Interrupt Polarity, and Range Register ... 38 SPI Protocol ... 25 Power Control Register ... 38 I2C Protocol ... 26 Self Test Register ... 39 Reading Acceleration or Temperature Data from the Interface Reset Register .. 39 ... 26 Recommended Soldering Profile ... 40 FIFO ... 27 PCB Footprint Pattern ... 41 Interrupts ... 28 Packaging and Ordering Information ... 42 DATA_RDY ... 28 Outline Dimensions ... 42 DRDY Pin .. 28 Branding Information .. 42 FIFO_FULL ... 28 Ordering Guide .. 42 FIFO_OVR .. 28 Activity ... 28
REVISION HISTORY 9/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 42 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ANALOG OUTPUT FOR THE ADXL354 DIGITAL OUTPUT FOR THE ADXL355 SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355 I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ROOT ALLAN VARIANCE (RAV) ADXL355 CHARACTERISTICS THEORY OF OPERATION ANALOG OUTPUT DIGITAL OUTPUT AXES OF ACCELERATION SENSITIVITY POWER SEQUENCING POWER SUPPLY DESCRIPTION VSUPPLY V1P8ANA V1P8DIG VDDIO OVERRANGE PROTECTION SELF TEST FILTER SERIAL COMMUNICATIONS SPI PROTOCOL I2C PROTOCOL READING ACCELERATION OR TEMPERATURE DATA FROM THE INTERFACE FIFO INTERRUPTS DATA_RDY DRDY PIN FIFO_FULL FIFO_OVR ACTIVITY NVM_BUSY EXTERNAL SYNCHRONIZATION AND INTERPOLATION EXT_SYNC = 00—No External Sync or Interpolation EXT_SYNC = 10—External Sync with Interpolation EXT_SYNC = 01—External Sync and External Clock ADXL355 REGISTER MAP REGISTER DEFINITIONS ANALOG DEVICES ID REGISTER Address: 0x00, Reset: 0xAD, Name: DEVID_AD ANALOG DEVICES MEMS ID REGISTER Address: 0x01, Reset: 0x1D, Name: DEVID_MST DEVICE ID REGISTER Address: 0x02, Reset: 0xED, Name: PARTID PRODUCT REVISION ID REGISTER Address: 0x03, Reset: 0x00, Name: REVID STATUS REGISTER Address: 0x04, Reset: 0x00, Name: STATUS FIFO ENTRIES REGISTER Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES TEMPERATURE DATA REGISTERS Address: 0x06, Reset: 0x00, Name: TEMP2 Address: 0x07, Reset: 0x00, Name: TEMP1 X-AXIS DATA REGISTERS Address: 0x08, Reset: 0x00, Name: XDATA3 Address: 0x09, Reset: 0x00, Name: XDATA2 Address: 0x0A, Reset: 0x00, Name: XDATA1 Y-AXIS DATA REGISTERS Address: 0x0B, Reset: 0x00, Name: YDATA3 Address: 0x0C, Reset: 0x00, Name: YDATA2 Address: 0x0D, Reset: 0x00, Name: YDATA1 Z-AXIS DATA REGISTERS Address: 0x0E, Reset: 0x00, Name: ZDATA3 Address: 0x0F, Reset: 0x00, Name: ZDATA2 Address: 0x10, Reset: 0x00, Name: ZDATA1 FIFO ACCESS REGISTER Address: 0x11, Reset: 0x00, Name: FIFO_DATA X-AXIS OFFSET TRIM REGISTERS Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L Y-AXIS OFFSET TRIM REGISTERS Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L Z-AXIS OFFSET TRIM REGISTERS Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L ACTIVITY ENABLE REGISTER Address: 0x24, Reset: 0x00, Name: ACT_EN ACTIVITY THRESHOLD REGISTERS Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L ACTIVITY COUNT REGISTER Address: 0x27, Reset: 0x01, Name: ACT_COUNT FILTER SETTINGS REGISTER Address: 0x28, Reset: 0x00, Name: Filter FIFO SAMPLES REGISTER Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES INTERRUPT PIN (INTx) FUNCTION MAP REGISTER Address: 0x2A, Reset: 0x00, Name: INT_MAP DATA SYNCHRONIZATION Address: 0x2B, Reset: 0x00, Name: Sync I2C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER Address: 0x2C, Reset: 0x81, Name: Range POWER CONTROL REGISTER Address: 0x2D, Reset: 0x01, Name: POWER_CTL SELF TEST REGISTER Address: 0x2E, Reset: 0x00, Name: SELF_TEST RESET REGISTER Address: 0x2F, Reset: 0x00, Name: Reset RECOMMENDED SOLDERING PROFILE PCB FOOTPRINT PATTERN PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS BRANDING INFORMATION ORDERING GUIDE