Datasheet ADXL350 (Analog Devices)

3-Axis, ±1g /±2g /±4g /±8g Digital Accelerometer Data Sheet ADXL350 FEATURES GENERAL DESCRIPTION Excellent zero-g bias accuracy and stability with
The high performance ADXL350 is a small, thin, low power,
minimum/maximum specifications
3-axis accelerometer with high resolution (13-bit) and selectable
Ultralow power: as low as 45 μA in measurement mode and
measurement ranges up to ±8 g. The ADXL350 offers industry-
0.1 μA in standby mode at VS = 2.5 V (typical)
leading noise and temperature performance for application
Power consumption scales automatically with bandwidth
robustness with minimal calibration. Digital output data is
User-selectable resolution
formatted as 16-bit twos complement and is accessible through
Fixed 10-bit resolution
either a SPI (3- or 4-wire) or I2C digital interface.
Full resolution, where resolution increases with g range,
The ADXL350 is well suited for high performance portable
up to 13-bit resolution at ±8 g (maintains 2 mg /LSB scale
applications. It measures the static acceleration of gravity in tilt-
factor in all g ranges)
sensing applications, as well as dynamic acceleration resulting
Embedded, 32-level FIFO buffer minimizes host processor
from motion or shock. Its high resolution (2 mg/LSB) enables
load
measurement of inclination changes of less than 1.0°.
Tap/double tap detection and free-fall detection Activity/inactivity monitoring
Several special sensing functions are provided. Activity and
Supply voltage range: 2.0 V to 3.6 V
inactivity sensing detect the presence or lack of motion and if
I/O voltage range: 1.7 V to V
the acceleration on any axis exceeds a user-set level. Tap sensing
S SPI (3- and 4-wire) and I2C digital interfaces
detects single and double taps. Free-fall sensing detects if the
Flexible interrupt modes mappable to either interrupt pin
device is falling. These functions can be mapped to one of two
Measurement ranges selectable via serial command
interrupt output pins.
Bandwidth selectable via serial command
Low power modes enable intelligent motion-based power
Wide temperature range (−40°C to +85°C)
management with threshold sensing and active acceleration
10,000 g shock survival
measurement at extremely low power dissipation.
Pb-free/RoHS compliant
The ADXL350 is supplied in a small, thin, 3 mm × 4 mm ×
Small and thin: 4 mm × 3 mm × 1.2 mm cavity LGA package
1.2 mm, 16-lead cavity laminate package.
APPLICATIONS Portable consumer devices High performance medical and industrial applications FUNCTIONAL BLOCK DIAGRAM VS VDD I/O ADXL350 POWER MANAGEMENT CONTROL INT1 SENSE ADC AND ELECTRONICS DIGITAL INTERRUPT 3-AXIS FILTER LOGIC INT2 SENSOR SDA/SDI/SDIO 32 LEVEL SERIAL I/O FIFO SDO/ALT ADDRESS SCL/SCLK
-001 71
GND CS
102 Figure 1.
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Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide