Datasheet ADXL344 (Analog Devices) - 10

Data Sheet ADXL344 40 40 35 35 ) ) % % ( 30 ( 30 TION TION A 25 25 L LA U PU 20 OP 20 PO F O T 15 T OF P 15 N EN E C C 10 R 10 E PER P 5 5 0 0
019
0.5 0.6 0.7 0.8 0.9 1.0
007
90 100 110 120 130 140 150 160 170 180 SELF-TEST SHIFT (g ) OUTPUT CURRENT (µA)
10628- 10628- Figure 16. X-Axis Self-Test Response at 25°C, VS = 2.6 V Figure 19. Supply Current at 25°C, 100 Hz Output Data Rate, VS = 2.6 V
40 160 35 140 ) % ( 30 120 A) µ TION ( A 25 100 L NT PU 20 80 PO F CURRE O Y T 15 L 60 P EN C UP S 10 40 PER 5 20 0 0 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5
008
3.13 6.25 12.50 25 50 100 200 400 800 1600 3200
020
SELF-TEST SHIFT (g )
10628-
OUTPUT DATA RATE (Hz)
10628- Figure 17. Y-Axis Self-Test Response at 25°C, VS = 2.6 V Figure 20. Supply Current vs. Output Data Rate at 25°C—10 Parts, VS = 2.6 V
40 150 35 A) µ 140 ) % N ( ( 30 IO T P TION 130 A 25 UM L NS PU 20 CO 120 PO F NT O T 15 EN 110 C CURRE 10 Y L PER P 100 UP 5 S 0 90 1.0 1.1 1.2 1.3 1.4 1.5
009
1.6 1.8 2.0 2.2 2.4 2.6 2.8
021
SELF-TEST SHIFT (g ) SUPPLY VOLTAGE, V
10628-
S (V)
10628- Figure 18. Z-Axis Self-Test Response at 25°C, VS = 2.6 V Figure 21. Supply Current vs. Supply Voltage at 25°C Rev. 0 | Page 9 of 40 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Autosleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY Bit SINGLE_TAP Bit DOUBLE_TAP Bit Activity Bit Inactivity Bit FREE_FALL Bit Watermark Bit Overrun Bit Orientation Bit FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Improved Tap Bit Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Register 0x3A—TAP_SIGN (Read Only) xSIGN Bits xTAP Bits Register 0x3B—ORIENT_CONF (Read/Write) INT_ORIENT Bit Dead Zone Bits INT_3D Bit Divisor Bits Register 0x3C—Orient (Read Only) Vx Bits xD_ORIENT Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Improved Tap Detection Tap Sign Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Orientation Sensing Data Formatting of Upper Data Rates Noise Performance Operation at Voltages Other Than 2.6 V Offset Performance at Lowest Data Rates Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide