Datasheet ADXL343 (Analog Devices)

3-Axis, ±2 g /±4 g /±8 g /±16 g Digital MEMS Accelerometer Data Sheet ADXL343 FEATURES GENERAL DESCRIPTION Multipurpose accelerometer with 10- to 13-bit resolution for
The ADXL343 is a versatile 3-axis, digital-output, low g MEMS
use in a wide variety of applications
accelerometer. Selectable measurement range and bandwidth, and
Digital output accessible via SPI (3- and 4-wire) and I2C
configurable, built-in motion detection make it suitable for sensing
Built-in motion detection features make tap, double-tap,
acceleration in a wide variety of applications. Robustness to
activity, inactivity, and free-fall detection trivial
10,000 g of shock and a wide temperature range (−40°C to +85°C)
User-adjustable thresholds
enable use of the accelerometer even in harsh environments.
Interrupts independently mappable to two interrupt pins
The ADXL343 measures acceleration with high resolution (13-bit)
Low power operation down to 23 µA and embedded FIFO for
measurement at up to ±16 g. Digital output data is formatted as
reducing overall system power
16-bit twos complement and is accessible through either an SPI
Wide supply voltage range: 2.0 V to 3.6 V
(3- or 4-wire) or I2C digital interface. The ADXL343 can
I/O voltage 1.7 V to VS
measure the static acceleration of gravity in tilt-sensing appli-
Wide operating temperature range (−40°C to +85°C)
cations, as well as dynamic acceleration resulting from motion
10,000 g shock survival
or shock. Its high resolution (3.9 mg/LSB) enables measurement
Small, thin, Pb free, RoHS compliant 3 mm × 5 mm × 1 mm
of inclination changes less than 1.0°.
LGA package
Several special sensing functions are provided. Activity and
APPLICATIONS
inactivity sensing detect the presence or lack of motion. Tap
Handsets
sensing detects single and double taps in any direction. Free-fall
Gaming and pointing devices
sensing detects if the device is falling. These functions can be
Hard disk drive (HDD) protection
mapped individual y to either of two interrupt output pins. An integrated memory management system with a 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption. The ADXL343 is supplied in a small, thin, 3 mm × 5 mm × 1 mm, 14-terminal, plastic package.
FUNCTIONAL BLOCK DIAGRAM VS VDD I/O ADXL343 POWER MANAGEMENT CONTROL INT1 SENSE ADC AND ELECTRONICS DIGITAL INTERRUPT 3-AXIS FILTER LOGIC INT2 SENSOR SDA/SDI/SDIO 32 LEVEL SERIAL I/O FIFO SDO/ALT ADDRESS SCL/SCLK
001
GND CS
10627- Figure 1.
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Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Data Formatting of Upper Data Rates Noise Performance Operation at Voltages Other Than 2.5 V Offset Performance at Lowest Data Rates Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide