Datasheet ADIS16228 (Analog Devices) - 10

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Data Sheet ADIS16228 BASIC OPERATION
The ADIS16228 uses a SPI for communication, which enables Table 8 provides a list of user registers with their lower byte a simple connection with a compatible, embedded processor addresses. Each register consists of two bytes that each has its own platform, as shown in Figure 8. The factory default configuration unique 7-bit address. Figure 9 relates the bits of each register to for DIO1 provides a busy indicator signal that transitions low their upper and lower addresses. when an event completes and data is available for user access.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Use the DIO_CTRL register (see Table 66) to reconfigure DIO1 009 and DIO2, if necessary.
UPPER BYTE LOWER BYTE
10069- Figure 9. Generic Register Bit Definitions
I/O LINES ARE COMPATIBLE WITH 3.3V 3.3V OR 5V LOGIC LEVELS VDD SPI WRITE COMMANDS 1 2
User control registers govern many internal operations. The
SYSTEM SS 14 CS PROCESSOR ADIS16228
DIN bit sequence in Figure 12 provides the ability to write to
SPI MASTER SCLK 13 SCLK
these registers, one byte at a time. Some configuration changes
MOSI 11 DIN
and functions require only one write cycle. For example, set
MISO 12 DOUT
GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a manual capture
IRQ2 7 DIO2
sequence. The manual capture starts immediately after the last bit
IRQ1 15 DIO1
clocks into DIN (16th SCLK rising edge). Other configurations may
3 4 5 8
008 require writing to both bytes. 10069-
CS
Figure 8. Electrical Hook-Up Diagram
SCLK Table 6. Generic Master Processor Pin Names and Functions
010
Pin Name Function DIN
10069- SS Slave select Figure 10. SPI Sequence for Manual Capture Start (DIN = 0xBF08) SCLK Serial clock
SPI READ COMMANDS
MOSI Master output, slave input MISO Master input, slave output A single register read requires two 16-bit SPI cycles that also IRQ1, IRQ2 Interrupt request inputs (optional) use the bit assignments that are shown in Figure 12. The first sequence sets R/W = 0 and communicates the target address The ADIS16228 SPI interface supports full duplex serial (Bits[A6:A0]). Bits[D7:D0] are don’t care bits for a read DIN communication (simultaneous transmit and receive) and uses sequence. DOUT clocks out the requested register contents the bit sequence shown in Figure 12. Table 7 provides a list of during the second sequence. The second sequence can also use the most common settings that require attention to initialize DIN to set up the next read. Figure 11 provides a signal diagram a processor serial port for the ADIS16228 SPI interface. for all four SPI signals while reading the PROD_ID. In this
Table 7. Generic Master Processor SPI Settings
diagram, DIN = 0x5600 and DOUT reflects the decimal
Processor Setting Description
equivalent of 16,228. Master The ADIS16228 operates as a slave.
CS
SCLK Rate ≤ 2.5 MHz Bit rate setting. SPI Mode 3 Clock polarity/phase
SCLK
(CPOL = 1, CPHA = 1).
DIN
MSB First Bit sequence. 16-Bit Shift register/data length.
DOUT
1 1 0
DOUT = 0011 1111 0110 0100 = 0x3F64 = 16,228 = PROD_ID
10069- Figure 11. Example SPI Read, PROD_ID, Second Sequence
CS SCLK DIN R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 R/W A6 A5 DOUT DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB15 DB14 DB13
012
NOTES 1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).
10069- Figure 12. Example SPI Read Sequence Rev. E | Page 9 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS THEORY OF OPERATION SENSING ELEMENT SIGNAL PROCESSING USER INTERFACE SPI Interface Dual-Memory Structure BASIC OPERATION SPI WRITE COMMANDS SPI READ COMMANDS DATA RECORDING AND SIGNAL PROCESSING RECORDING MODE Manual FFT Mode Automatic FFT Mode Manual Time Capture Mode Real-Time Mode SPECTRAL RECORD PRODUCTION SAMPLE RATE/FILTERING DYNAMIC RANGE/SENSITIVITY Frequency Response Correction Axial Definitions Dynamic Range Settings Scale Adjustment PRE-FFT WINDOWING FFT FFT Averaging RECORDING TIMES DATA RECORDS FFT RECORD FLASH ENDURANCE SPECTRAL ALARMS ALARM DEFINITION Alarm Band Frequency Definitions Alarm Trigger Settings Enable Alarm Settings ALARM INDICATOR SIGNALS ALARM FLAGS AND CONDITIONS ALARM STATUS WORST-CASE CONDITION MONITORING READING OUTPUT DATA READING DATA FROM THE DATA BUFFER ACCESSING FFT RECORD DATA DATA FORMAT REAL-TIME DATA COLLECTION POWER SUPPLY/TEMPERATURE FFT EVENT HEADER SYSTEM TOOLS GLOBAL COMMANDS STATUS/ERROR FLAGS POWER-DOWN OPERATION MANAGMENT Software Busy Indicator Software Escape Code INPUT/OUTPUT FUNCTIONS Busy Indicator Trigger Input Alarm Indicator General-Purpose Input/Output SELF-TEST FLASH MEMORY MANAGEMENT DEVICE IDENTIFICATION APPLICATIONS INFORMATION INTERFACE BOARD FLEX CONNECTOR CARE MATING CONNECTOR OUTLINE DIMENSIONS ORDERING GUIDE