Datasheet ADIS16240 (Analog Devices) - 10

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Data Sheet ADIS16240 BASIC OPERATION
The ADIS16240 starts up automatically when it has a valid power User registers govern all data collection and configuration. Table 7 supply and begins producing digital acceleration data in the output provides a memory map that includes all user registers, along with registers. When using the factory-default configuration, DIO1 references to bit assignment tables that follow the generic assign- serves as a data-ready indicator signal that can drive a processor ments in Figure 15. interrupt function. Figure 14 shows a schematic for connecting to a SPI-compatible processor platform, referred to as the SPI
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 01 master.
UPPER BYTE LOWER BYTE
33- 81 0
VDD VDD
Figure 15. Generic Register Bit Assignments
SPI Write Commands SYSTEM PROCESSOR ADIS16240 SPI MASTER SPI SLAVE
Master processors write to the control registers, one byte at a
SS CS
time, using the bit assignments shown in Figure 18. The program-
SCLK SCLK
mable registers in Table 7 provide controls for optimizing sensor
MOSI DIN
operation and for starting various automated functions. For
MISO DOUT
example, set GLOB_CMD[8] = 1 (DIN = 0xCB01) to wake up the
IRQ1 DIO1
device.
IRQ2 DIO2 CS
10 0 3-
SCLK
13 08 12 0 3- Figure 14. Electrical Hook-Up Diagram
DIN
13 08
Table 5. Generic Master Processor Pin Names and Functions
Figure 16. SPI Sequence for a Wake-Up Command (DIN = 0xCB01)
Pin Name Function
Some configurations require writing both bytes to a register, SS Slave select. which takes two separate 16-bit sequences. See GLOB_CMD[3] IRQ1, IRQ2 Interrupt request inputs. in Table 24 for backing up configuration data in nonvolatile MOSI Master output, slave input. flash memory. MISO Master input, slave output.
SPI Read Commands
SCLK Serial clock. Reading data on the SPI requires two consecutive 16-bit The ADIS16240 SPI interface supports full duplex serial commu- sequences. The first sequence transmits the read command on nication (simultaneous transmit and receive) and uses the bit DIN, and the second sequence receives the resulting data from sequence shown in Figure 18. Processor platforms typically DOUT. The 7-bit register address can represent either the upper support SPI communication with general-purpose serial ports that or lower byte address for the target register. For example, DIN require some configuration in their control registers. Table 6 lists can be either 0x0200 or 0x0300 when reading the SUPPLY_OUT the most common settings that require attention when register. The SPI operates in full duplex mode, which means that initializing a pro-cessor serial port for communication with the the master processor can read the output data from DOUT while ADIS16240. using the same SCLK pulses to transmit a new command on DIN. In Figure 17, the second SPI segment sets up the device to
Table 6. Generic Master Processor SPI Settings
read YACCL_OUT on the following SPI segment (not shown).
Processor Setting Description
Master The ADIS16240 operates as a slave. SCLK Rate ≤ 2.5 MHz Bit rate setting. SPI Mode 3 (1,1) Clock polarity/phase (CPOL = 1, CPHA = 1). MSB First Bit sequence. 16-Bit Shift register/data length.
SPI SEGMENT 1 SPI SEGMENT 2 CS SCLK DIN = 0x0600 TO READ YACCL_OUT DIN DOUT
13 0 3-
DIN = 0x0400 PRODUCES XACCL_OUT CONTENTS ON DOUT = 0x802B = 2.21g , NEW DATA
813 0
DOUT DURING THE NEXT SPI SEGMENT
Figure 17. Example SPI Read Sequence Rev. C | Page 9 of 20 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Sensing Element Data Sampling and Processing User Interface SPI Interface User Registers Capture Basic Operation SPI Write Commands Memory Map Output Data Registers Processing Sensor Data Event Recorder Internal Trigger Setup External Trigger Setup Buffer Memory Configuration Event Organization Reading Event Data Transient Behavior During Capture Operational Control Internal Sample Rate Global Commands Input/Output Lines Offset Adjustment Diagnostics Clock Checksum Flash Memory Endurance Management Applications Information Assembly Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide