Datasheet ICM7242 (Intersil) - 4

link to page 7 link to page 4 link to page 4 ICM7242
Test Circuit VDD 1 8 TIME BASE INPUT/OUTPUT ÷21 (RC/2) OUTPUT 2 7 VDD R ÷28 (RC/256) OUTPUT 3 6 C 4 5 RESET TRIGGER TIME BASE PERIOD = 1.0RC; 1s = 1M x 1µF
NOTE: 4. 21 and 28 outputs are inverters and have active pullups.
Application Information
external resistors used for the 2242 will not be required for the ICM7242. The ICM7242 will, however, plug into a socket
Operating Considerations
for the 2242 having these resistors. Shorting the RC terminal or output terminals to VDD may The timing diagram for the ICM7242 is shown in Figure 1. exceed dissipation ratings and/or maximum DC current limits Assuming that the device is in the RESET mode, which (especially at high supply voltages). occurs on power up or after a positive signal on the RESET There is a limitation of 50pF maximum loading on the TB I/O terminal (if TRIGGER is low), a positive edge on the trigger terminal if the timebase is being used to drive the counter input signal will initiate normal operation. The discharge section. If higher value loading is used, the counter sections transistor turns on, discharging the timing capacitor C, and may miscount. all the flip-flops in the counter chain change states. Thus, the outputs on terminals 2 and 3 change from high to low states. For greatest accuracy, use timing component values shown After 128 negative timebase edges, the 28 output returns to in Figure 8. For highest frequency operation it will be the high state. desirable to use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200kHz. The timing capacitor should be connected between the RC
TRIGGER INPUT
pin and the positive supply rail, V
(TERMINAL 6)
DD, as shown in Figure 1. When system power is turned off, any charge remaining on
TIMEBASE INPUT
the capacitor will be discharged to ground through a large
(TERMINAL 8)
internal diode between the RC node and VSS. Do NOT
÷2 OUTPUT
reference the timing capacitor to ground, since there is no
(TERMINAL 2)
high current path in this direction to safely discharge the
÷128/256 OUTPUT
capacitor when power is turned off. The discharge current
(TERMINAL 3) (ASTABLE
from such a configuration could potentially damage the
OR “FREE RUN” MODE) 128RC 128RC
device.
÷128/256 OUTPUT (TERMINAL 3)
When driving the counter section from an external clock, the
(MONOSTABLE 128RC OR “ONE SHOT” MODE)
optimum drive waveform is a square wave with an amplitude equal to the supply voltage. If the clock is a very slow ramp
FIGURE 1. TIMING DIAGRAMS OF OUTPUT WAVEFORMS
triangular, sine wave, etc., it will be necessary to “square up”
FOR THE ICM7242 (COMPARE WITH FIGURE 5)
the waveform; this can be done by using two CMOS
VDD fIN >3/
inverters in series, operating from the same supply voltage
4 (V+) 1 8 <1/4 (V+)
as the ICM7242.
fIN/2 2 7
The ICM7242 is a non-programmable timer whose principal
OUTPUTS fIN/256 3 6
applications will be very low frequency oscillators and long
VDD 4 5
range timers; it makes a much better low frequency oscillator/timer than a 555 or ICM7555, because of the on- chip 8-bit counter. Also, devices can be cascaded to produce extremely low frequency signals.
FIGURE 2. USING THE ICM7242 AS A RIPPLE COUNTER (DIVIDER)
Because outputs will not be ANDed, output inverters are used instead of open drain N-Channel transistors, and the FN2866 Rev 5.00 Page 4 of 11 September 14, 2015