Datasheet ADIS16362 (Analog Devices) - 5

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ADIS16362 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
DAC OUTPUT 5 kΩ/100 pF to GND Resolution 12 Bits Relative Accuracy 101 LSB ≤ input code ≤ 4095 LSB ±4 LSB Differential Nonlinearity ±1 LSB Offset Error ±5 mV Gain Error ±0.5 % Output Range 0 3.3 V Output Impedance 2 Ω Output Settling Time 10 µs LOGIC INPUTS1 Input High Voltage, V 2.0 V IH Input Low Voltage, V 0.8 V IL CS signal to wake up from sleep mode 0.55 V CS Wake-Up Pulse Width 20 µs Logic 1 Input Current, I V = 3.3 V ±0.2 ±10 µA IH IH Logic 0 Input Current, I V = 0 V IL IL All Pins Except RST 40 60 μA RST Pin 1 mA Input Capacitance, C 10 pF IN DIGITAL OUTPUTS1 Output High Voltage, V I = 1.6 mA 2.4 V OH SOURCE Output Low Voltage, V I = 1.6 mA 0.4 V OL SINK FLASH MEMORY Endurance2 10,000 Cycles Data Retention3 T = 85°C 20 Years J FUNCTIONAL TIMES4 Time until data is available Power-On Start-Up Time Normal mode, SMPL_PRD ≤ 0x09 180 ms Low power mode, SMPL_PRD ≥ 0x0A 250 ms Reset Recovery Time Normal mode, SMPL_PRD ≤ 0x09 60 ms Low power mode, SMPL_PRD ≥ 0x0A 130 ms Sleep Mode Recovery Time Normal mode, SMPL_PRD ≤ 0x09 4 ms Low power mode, SMPL_PRD ≥ 0x0A 9 ms Flash Memory Test Time Normal mode, SMPL_PRD ≤ 0x09 17 ms Low power mode, SMPL_PRD ≥ 0x0A 90 ms Automatic Self-Test Time SMPL_PRD = 0x01 12 ms CONVERSION RATE SMPL_PRD = 0x01 to 0xFF 0.413 819.2 SPS Clock Accuracy ±3 % Sync Input Clock 0.85 1.2 kHz POWER SUPPLY Operating voltage range, VCC 4.75 5.0 5.25 V Power Supply Current Low power mode 24 mA Normal mode 49 mA Sleep mode 500 µA 1 The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant. 2 Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C. 3 The data retention lifetime equivalent is at a junction temperature (TJ) of 85°C as per JEDEC Standard 22, Method A117. Data retention lifetime decreases with junction temperature. 4 These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may affect overall accuracy. 5 The sync input clock functions below the specified minimum value, at reduced performance levels. Rev. E | Page 4 of 20 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Operation Reading Sensor Data Device Configuration Memory Map Burst Read Data Collection Output Data Registers Calibration Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) Operational Control Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range Input/Output Functions General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Installation/Handling Gyroscope Bias Optimization Input ADC Channel Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide