Datasheet ADIS16360, ADIS16365 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Six Degrees of Freedom Inertial Sensor |
| 页数 / 页 | 20 / 5 — Data Sheet. ADIS16360/ADIS16365. TIMING SPECIFICATIONS. Table 2. Normal … |
| 修订版 | E |
| 文件格式/大小 | PDF / 389 Kb |
| 文件语言 | 英语 |
Data Sheet. ADIS16360/ADIS16365. TIMING SPECIFICATIONS. Table 2. Normal Mode. Low Power Mode. (SMPL_PRD ≤ 0x09). (SMPL_PRD ≥ 0x0A)
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Data Sheet ADIS16360/ADIS16365 TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2. Normal Mode Low Power Mode (SMPL_PRD ≤ 0x09) (SMPL_PRD ≥ 0x0A) Burst Read Parameter Description Min1 Typ Max Min
1
Typ Max Min
1
Typ Max Unit
f Serial clock 0.01 2.0 0.01 0.3 0.01 1.0 MHz SCLK t Stall period between data 9 75 1/f µs STALL SCLK t Read rate 40 100 µs READRATE t Chip select to SCLK edge 48.8 48.8 48.8 ns CS t DOUT valid after SCLK edge 100 100 100 ns DAV t DIN setup time before SCLK rising edge 24.4 24.4 24.4 ns DSU t DIN hold time after SCLK rising edge 48.8 48.8 48.8 ns DHD t , t SCLK rise/fall times 5 12.5 5 12.5 5 12.5 ns SCLKR SCLKF t , t DOUT rise/fall times 5 12.5 5 12.5 5 12.5 ns DR DF t SFS CS high after SCLK edge 5 5 5 ns t Input sync positive pulse width 5 5 µs 1 t Input sync low time 100 100 µs x t Input sync to data ready output 600 600 µs 2 t Input sync period 833 833 µs 3 1 Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
002 07570- Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS SCLK
003 07570- Figure 3. Stall Time and Data Rate
t3 t2 t t 1 X SYNC CLOCK (DIO4)
004
DATA READY
07570- Figure 4. Input Clock Timing Diagram Rev. E | Page 5 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Operation Reading Sensor Data Device Configuration Memory Map Burst Read Data Collection Output Data Registers Calibration Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) Operational Control Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range Input/Output Functions General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Installation/Handling Gyroscope Bias Optimization Input ADC Channel Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide
Data Sheet ADIS16360/ADIS16365 TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2. Normal Mode Low Power Mode (SMPL_PRD ≤ 0x09) (SMPL_PRD ≥ 0x0A) Burst Read Parameter Description Min1 Typ Max Min
1
Typ Max Min
1
Typ Max Unit
f Serial clock 0.01 2.0 0.01 0.3 0.01 1.0 MHz SCLK t Stall period between data 9 75 1/f µs STALL SCLK t Read rate 40 100 µs READRATE t Chip select to SCLK edge 48.8 48.8 48.8 ns CS t DOUT valid after SCLK edge 100 100 100 ns DAV t DIN setup time before SCLK rising edge 24.4 24.4 24.4 ns DSU t DIN hold time after SCLK rising edge 48.8 48.8 48.8 ns DHD t , t SCLK rise/fall times 5 12.5 5 12.5 5 12.5 ns SCLKR SCLKF t , t DOUT rise/fall times 5 12.5 5 12.5 5 12.5 ns DR DF t SFS CS high after SCLK edge 5 5 5 ns t Input sync positive pulse width 5 5 µs 1 t Input sync low time 100 100 µs x t Input sync to data ready output 600 600 µs 2 t Input sync period 833 833 µs 3 1 Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
002 07570- Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS SCLK
003 07570- Figure 3. Stall Time and Data Rate
t3 t2 t t 1 X SYNC CLOCK (DIO4)
004
DATA READY
07570- Figure 4. Input Clock Timing Diagram Rev. E | Page 5 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Operation Reading Sensor Data Device Configuration Memory Map Burst Read Data Collection Output Data Registers Calibration Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) Operational Control Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range Input/Output Functions General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Installation/Handling Gyroscope Bias Optimization Input ADC Channel Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide