Datasheet ADIS16360, ADIS16365 (Analog Devices) - 9

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Data Sheet ADIS16360/ADIS16365 THEORY OF OPERATION BASIC OPERATION
The user registers provide addressing for all input/output The ADIS16360/ADIS16365 are autonomous sensor systems operations on the SPI interface. Each 16-bit register has two that start up after they have a valid power supply voltage and 7-bit addresses: one for its upper byte and one for its lower begin producing inertial measurement data at the factory default byte. Table 8 lists the lower byte address for each register, and sample rate setting of 819.2 SPS. After each sample cycle, the Figure 10 shows the generic bit assignments. sensor data is loaded into the output registers, and DIO1 pulses
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
high, which provides a new data ready control signal for driving 010 system-level interrupt service routines. In a typical system, a
UPPER BYTE LOWER BYTE
07570- master processor accesses the output data registers through the Figure 10. Generic Register Bit Assignments SPI interface, using the connection diagram shown in Figure 9.
READING SENSOR DATA
Table 6 provides a generic functional description for each pin on Although the ADIS16360/ADIS16365 produce data indepen- the master processor. Table 7 describes the typical master processor dently, they operate as SPI slave devices that communicate with settings that are normal y found in a configuration register and system (master) processors using the 16-bit segments displayed used for communicating with the ADIS16360/ADIS16365. in Figure 11. Individual register reads require two of these 16-bit
I/O LINES ARE COMPATIBLE WITH 5V 3.3V OR 5V LOGIC LEVELS
sequences. The first 16-bit sequence contains the read command
VDD
bit (R/W = 0) and the target register address (A6 to A0); the last
10 11 12
eight bits are “don’t care” bits when requesting a read. The second
SYSTEM PROCESSOR SS 6 CS ADIS16360/
16-bit sequence transmits the register contents (D15 to D0) on
SPI MASTER ADIS16365 SCLK 3 SCLK SPI SLAVE
the DOUT line. For example, if DIN = 0x0A00, the contents of
MOSI 5 DIN
the XACCL_OUT register are shifted out on the DOUT line
MISO 4 DOUT
during the next 16-bit sequence.
IRQ 7 DIO1
The SPI operates in ful -duplex mode, which means that the
13 14 15
master processor can read the output data from DOUT while 009 using the same SCLK pulses to transmit the next target address 07570- Figure 9. Electrical Connection Diagram on DIN.
DEVICE CONFIGURATION Table 6. Generic Master Processor Pin Names and Functions Pin Name Function
The user register memory map (see Table 8) identifies configu- SS Slave select ration registers with either a W or R/W. Configuration commands SCLK Serial clock also use the bit sequence shown in Figure 11. If the MSB = 1, the MOSI Master output, slave input last eight bits (DC7 to DC0) in the DIN sequence are loaded into MISO Master input, slave output the memory address associated with the address bits (A6 to A0). IRQ Interrupt request For example, if DIN = 0xA11F, 0x1F is loaded into Address 0x21 (XACCL_OFF, upper byte) at the conclusion of the data frame.
Table 7. Generic Master Processor SPI Settings
The master processor initiates the backup function by setting
Processor Setting Description
GLOB_CMD[3] = 1 (DIN = 0xBE08). This command copies Master The ADIS16360/ADIS16365 operate as slaves the user registers into their assigned flash memory locations SCLK Rate ≤ 2 MHz1 Normal mode, SMPL_PRD[7:0] ≤ 0x09 and requires the power supply to stay within its normal operating SPI Mode 3 CPOL = 1 (polarity), CPHA = 1 (phase) range for the entire 50 ms process. The FLASH_CNT register MSB First Mode Bit sequence provides a running count of these events for monitoring the 16-Bit Mode Shift register/data length long-term reliability of the flash memory. 1 For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz.
CS SCLK DIN R/W R/W A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 A6 A5 DOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 NOTES 1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]
1 1
IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.
0
2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.
07570- Figure 11. SPI Communication Bit Sequence Rev. E | Page 9 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Operation Reading Sensor Data Device Configuration Memory Map Burst Read Data Collection Output Data Registers Calibration Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) Operational Control Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range Input/Output Functions General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Installation/Handling Gyroscope Bias Optimization Input ADC Channel Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide