Datasheet ADXRS450 (Analog Devices) - 10

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Data Sheet ADXRS450 THEORY OF OPERATION
The ADXRS450 operates on the principle of a resonator gyro-
CONTINUOUS SELF-TEST
scope. A simplified version of one of four polysilicon sensing The ADXRS450 gyroscope uses a complete electromechanical structures is shown in Figure 16. Each sensing structure contains self-test. An electrostatic force is applied to the gyroscope frame, a dither frame that is electrostatically driven to resonance. This resulting in a deflection of the capacitive sense fingers. This produces the necessary velocity element to produce a Coriolis deflection is exactly equivalent to deflection that occurs as a force when experiencing angular rate. In the SOIC_CAV package, result of external rate input. The output from the beam structure is the ADXRS450 is designed to sense a z-axis (yaw) angular rate; processed by the same signal chain as a true rate output signal, whereas the vertical mount package (LCC_V) orients the device providing complete coverage of the electrical and mechanical such that it can sense pitch or roll angular rate on the same PCB. components. When the sensing structure is exposed to angular rate, the The electromechanical self-test is performed continuously during resulting Coriolis force couples into an outer sense frame, operation at a rate higher than the output bandwidth of the which contains movable fingers that are placed between fixed device. The self-test routine generates equivalent positive and pickoff fingers. This forms a capacitive pickoff structure that negative rate deflections. This information can then be filtered senses Coriolis motion. The resulting signal is fed to a series of with no overal effect on the demodulated rate output. gain and demodulation stages that produce the electrical rate signal output. The quad sensor design rejects linear and angular acceleration, including external g-forces and vibration. This is achieved by mechanical y coupling the four sensing structures such that external g-forces appear as common-mode signals that can be removed by the fully differential architecture
RATE SIGNAL WITH CONTINUOUS SELF TEST SIGNAL.
implemented in the ADXRS450.
SELF TEST AMPLITUDE. INTERNALLY LOW FREQUENCY RATE INFORMATION.
012
COMPARED TO THE SPECIFICATION TABLE LIMITS.
08952- Figure 17. Continuous Self-Test Demodulation
X
The difference amplitude between the positive and negative
Y
self-test deflections is filtered to 2 Hz, and it is continuously
Z
monitored and compared to hardcoded self-test limits. If the measured amplitude exceeds these limits (listed in Table 1), one of two error conditions asserts depending on the magnitude of self-test error. For less severe self-test error magnitudes, the CST bit of the fault register is asserted; however, the status bits (ST[1:0]) in the sensor data response remain set to 0b01 for valid sensor data. For more severe self-test errors, the CST bit of the fault reg- ister is asserted, and the status bits (ST[1:0]) in the sensor data 1 1 0 response are set to 0b00 for invalid sensor data. Table 1 lists the 08952- thresholds for both of these failure conditions. If desired, the user Figure 16. Simplified Gyroscope Sensing Structure can access the self-test information by issuing a read command to the self-test memory register (Address 0x04). For more infor- The resonator requires 22.5 V (typical) for operation. Because mation about error reporting, see the SPI Communication Protocol only 5 V is typically available in most applications, a switching section. regulator is included on chip. Rev. C | Page 9 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide