Datasheet ADIS16060 (Analog Devices) - 10

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Data Sheet ADIS16060 THEORY OF OPERATION
The ADIS16060 operates on the principle of a resonator During the acquisition phase, the impedance model for AINx gyroscope. Two polysilicon sensing structures each contain a is a paral el combination of the capacitor CPIN and the network dither frame that is electrostatically driven to resonance. This formed by the series connection of RIN and CIN. CPIN is primarily generates the necessary velocity element to produce a Coriolis the pin capacitance. RIN is typical y 600 Ω and is a lumped force while rotating. At two of the outer extremes of each frame, component made up of some serial resistors and the on orthogonal to the dither motion, are movable fingers that are resistance of the switches. CIN is typical y 30 pF and mainly placed between fixed pickoff fingers to form a capacitive pickoff functions as the ADC sampling capacitor. structure that senses Coriolis motion. During the conversion phase, when the switches are open, the The resulting signal is fed to a series of gain and demodulation input impedance is limited to CPIN. RIN and CIN make a 1-pole, stages that produce the electrical rate signal output. The rate low-pass filter that reduces undesirable aliasing effects and signal is then converted to a digital representation of the limits the noise. output on the SPI pins. The dual-sensor design provides When the source impedance of the driving circuit is low, the linear acceleration (vibration, shock) rejection. Fabricating ADC input can be driven directly. Large source impedances the sensor with the signal-conditioning electronics preserves significantly affect the ac performance, especial y THD. The signal integrity in noisy environments. dc performances are less sensitive to the input impedance. The electrostatic resonator requires 14 V to 16 V for operation.
RATE SENSITIVE AXIS
Because only 5 V is typically available in most applications, a
RATE
charge pump is included on chip. After the demodulation stage,
AXIS
a single-pole, low-pass filter on the chip is used to limit high
LONGITUDINAL POSITIVE AXIS
frequency artifacts before final amplification. The frequency
MEASUREMENT DIRECTION
response is dominated by the second low-pass filter, which is
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set by adding capacitance across RATE and FILT.
1 4 5
019
ANALOG-TO-DIGITAL CONVERTER INPUT LATERAL AXIS
07103- Figure 12 shows an equivalent circuit of the input structure of Figure 13. Rate Signal Increases with Clockwise Rotation the ADIS16060 auxiliary ADC. The two diodes, D1 and D2, provide ESD protection for the analog inputs, AINx (AIN1 and AIN2). Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V, because exceeding this level causes these diodes to become forward-biased and to start conducting current. However, these diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions may eventually occur when the input signals exceed either VCC or GND.
VDD D1 R CIN IN AINx CPIN D2
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GND
-01 3 0 1 07 Figure 12. Equivalent Analog Input Circuit Rev. A | Page 9 of 12 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converter Input Rate Sensitive Axis Basic Operation Serial Peripheral Interface (SPI) Selecting Output Data Output Data Access Output Data Formatting ADC Conversion Applications Information Supply And Common Considerations Setting Bandwidth Increasing Measurement Range Dynamic Digital Sensitivity Scaling Temperature Measurements Self-Test Function Outline Dimensions Ordering Guide