Datasheet CA3140, CA3140A (Intersil) - 6

CA3140, CA3140A Application Information
When the CA3140 is operating such that output Terminal 6 is sinking current to the V- bus, transistor Q
Circuit Description
16 is the current sinking element. Transistor Q16 is mirror connected to D6, R7, As shown in the block diagram, the input terminals may be with current fed by way of Q21, R12, and Q20. Transistor Q20, in operated down to 0.5V below the negative supply rail. Two turn, is biased by current flow through R13, zener D8, and R14. class A amplifier stages provide the voltage gain, and a The dynamic current sink is controlled by voltage level sensing. unique class AB amplifier stage provides the current gain For purposes of explanation, it is assumed that output Terminal necessary to drive low-impedance loads. 6 is quiescently established at the potential midpoint between A biasing circuit provides control of cascoded constant current the V+ and V- supply rails. When output current sinking mode flow circuits in the first and second stages. The CA3140 operation is required, the collector potential of transistor Q13 is includes an on chip phase compensating capacitor that is driven below its quiescent level, thereby causing Q17, Q18 to sufficient for the unity gain voltage follower configuration. decrease the output voltage at Terminal 6. Thus, the gate terminal of PMOS transistor Q
Input Stage
21 is displaced toward the V- bus, thereby reducing the channel resistance of Q21. As a The schematic diagram consists of a differential input stage consequence, there is an incremental increase in current flow using PMOS field-effect transistors (Q9, Q10) working into a through Q20, R12, Q21, D6, R7, and the base of Q16. As a mirror pair of bipolar transistors (Q11, Q12) functioning as load result, Q16 sinks current from Terminal 6 in direct response to resistors together with resistors R2 through R5. The mirror pair the incremental change in output voltage caused by Q18. This transistors also function as a differential-to-single-ended sink current flows regardless of load; any excess current is converter to provide base current drive to the second stage internally supplied by the emitter-follower Q18. Short circuit bipolar transistor (Q13). Offset nulling, when desired, can be protection of the output circuit is provided by Q19, which is effected with a 10kΩ potentiometer connected across driven into conduction by the high voltage drop developed Terminals 1 and 5 and with its slider arm connected to Terminal across R11 under output short circuit conditions. Under these 4. Cascode-connected bipolar transistors Q2, Q5 are the conditions, the collector of Q19 diverts current from Q4 so as to constant current source for the input stage. The base biasing reduce the base current drive from Q17, thereby limiting current circuit for the constant current source is described flow in Q18 to the short circuited load terminal. subsequently. The small diodes D3, D4, D5 provide gate oxide protection against high voltage transients, e.g., static electricity.
Bias Circuit
Quiescent current in all stages (except the dynamic current
Second Stage
sink) of the CA3140 is dependent upon bias current flow in R1. Most of the voltage gain in the CA3140 is provided by the The function of the bias circuit is to establish and maintain second amplifier stage, consisting of bipolar transistor Q13 constant current flow through D1, Q6, Q8 and D2. D1 is a diode and its cascode connected load resistance provided by connected transistor mirror connected in parallel with the base bipolar transistors Q3, Q4. On-chip phase compensation, emitter junctions of Q1, Q2, and Q3. D1 may be considered as a sufficient for a majority of the applications is provided by C1. current sampling diode that senses the emitter current of Q6 Additional Miller-Effect compensation (roll off) can be and automatically adjusts the base current of Q6 (via Q1) to accomplished, when desired, by simply connecting a small maintain a constant current through Q6, Q8, D2. The base capacitor between Terminals 1 and 8. Terminal 8 is also currents in Q2, Q3 are also determined by constant current flow used to strobe the output stage into quiescence. When D1. Furthermore, current in diode connected transistor Q2 terminal 8 is tied to the negative supply rail (Terminal 4) by establishes the currents in transistors Q14 and Q15. mechanical or electrical means, the output Terminal 6 swings low, i.e., approximately to Terminal 4 potential.
Typical Applications Output Stage
Wide dynamic range of input and output characteristics with The CA3140 Series circuits employ a broad band output stage the most desirable high input impedance characteristics is that can sink loads to the negative supply to complement the achieved in the CA3140 by the use of an unique design based capability of the PMOS input stage when operating near the upon the PMOS Bipolar process. Input common mode voltage negative rail. Quiescent current in the emitter-follower cascade range and output swing capabilities are complementary, circuit (Q17, Q18) is established by transistors (Q14, Q15) allowing operation with the single supply down to 4V. whose base currents are “mirrored” to current flowing through The wide dynamic range of these parameters also means diode D2 in the bias circuit section. When the CA3140 is that this device is suitable for many single supply operating such that output Terminal 6 is sourcing current, applications, such as, for example, where one input is driven transistor Q18 functions as an emitter-follower to source current below the potential of Terminal 4 and the phase sense of the from the V+ bus (Terminal 7), via D7, R9, and R11. Under these output signal must be maintained – a most important conditions, the collector potential of Q13 is sufficiently high to consideration in comparator applications. permit the necessary flow of base current to emitter follower Q17 which, in turn, drives Q18. 6 FN957.10 July 11, 2005