Datasheet AD8451 (Analog Devices) - 5

AD8451 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
Reference Input Voltage Range BVREFH and BVREFL pins tied together AVEE AVCC V Output Voltage Level Shift BVREFL pin grounded Maximum BVREFH pin connected to VREF pin 4.5 5 5.5 mV Scale Factor VBVMEA/VBVREFH 1.8 2 2.2 mV/V CMRR ΔVCM = 10 V, RTO 80 dB Temperature Coefficient TA = TMIN to TMAX 0.05 µV/V/°C PSRR ΔVS = 20 V, RTO 100 dB Output Voltage Noise f = 1 kHz, RTI 105 nV/√Hz Voltage Noise, Peak to Peak f = 0.1 Hz to 10 Hz, RTI 2 µV p-p Small Signal −3 dB Bandwidth 1 MHz Slew Rate 0.8 V/µs CONSTANT CURRENT AND CONSTANT VOLTAGE LOOP FILTER AMPLIFIERS Offset Voltage 150 µV Offset Voltage Drift TA = TMIN to TMAX 0.6 µV/°C Input Bias Current −5 +5 nA Over Temperature TA = TMIN to TMAX −5 +5 nA Input Common-Mode Voltage Range AVEE + 1.5 AVCC − 1.8 V Output Voltage Swing VVCLN = AVEE + 1 V, VVCLP = AVCC − 1 V AVEE + 1.5 AVCC − 1 V Over Temperature TA = TMIN to TMAX AVEE + 1.7 AVCC − 1 V Closed-Loop Output Impedance 0.01 Ω Capacitive Load Drive 1000 pF Source Short-Circuit Current 1 mA Sink Short-Circuit Current 40 mA Open-Loop Gain 140 dB CMRR ΔVCM = 10 V 100 dB PSRR ΔVS = 20 V 100 dB Voltage Noise f = 1 kHz 10 nV/√Hz Voltage Noise, Peak to Peak f = 0.1 Hz to 10 Hz 0.3 µV p-p Current Noise f = 1 kHz 80 fA/√Hz Current Noise, Peak to Peak f = 0.1 Hz to 10 Hz 5 pA p-p Small Signal Gain Bandwidth Product 3 MHz Slew Rate ΔVVINT = 10 V 1 V/µs CC to CV Transition Time 1.5 µs VINT AND CONSTANT VOLTAGE BUFFER Nominal Gain 1 V/V Offset Voltage 150 µV Offset Voltage Drift TA = TMIN to TMAX 0.6 µV/°C Input Bias Current CV buffer only −5 +5 nA Over Temperature TA = TMIN to TMAX −5 +5 nA Input Voltage Range AVEE + 1.5 AVCC − 1.8 V Output Voltage Swing Current Sharing and Constant Voltage Buffers AVEE + 1.5 AVCC − 1.5 V Over Temperature TA = TMIN to TMAX AVEE + 1.7 AVCC − 1.5 V VINT Buffer VVCLN − 0.6 VVCLP + 0.6 V Over Temperature TA = TMIN to TMAX VVCLN − 0.6 VVCLP + 0.6 V Output Clamps Voltage Range VINT buffer only VCLP Pin VVCLN AVCC − 1 V VCLN Pin AVEE + 1 VVCLP V Closed-Loop Output Impedance 1 Ω Capacitive Load Drive 1000 pF Short-Circuit Current 40 mA PSRR ΔVS = 20 V 100 dB Rev. 0 | Page 4 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS IA CHARACTERISTICS DA CHARACTERISTICS CC AND CV LOOP FILTER AMPLIFIERS, AND VSET BUFFER VINT BUFFER REFERENCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW INSTRUMENTATION AMPLIFIER (IA) Reversing Polarity When Charging and Discharging IA Offset Option Battery Reversal and Overvoltage Protection DIFFERENCE AMPLIFIER (DA) CC AND CV LOOP FILTER AMPLIFIERS Compensation VINT Buffer MODE PIN, CHARGE AND DISCHARGE CONTROL APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION POWER SUPPLY CONNECTIONS CURRENT SENSE IA CONNECTIONS Current Sensors Optional Low-Pass Filter VOLTAGE SENSE DA CONNECTIONS Reverse Battery Conditions BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET) LOOP FILTER AMPLIFIERS CONNECTING TO A PWM CONTROLLER (VCTRL PIN) STEP-BY-STEP DESIGN EXAMPLE Step 1: Design the Switching Power Converter Step 2: Identify the Control Voltage Range of the ADP1972 Step 3: Determine the Control Voltage for the CV Loop Step 4: Determine the Control Voltage for the CC Loop and the Shunt Resistor Step 5: Choose the Control Voltage Sources Step 6: Select the Compensation Devices EVALUATION BOARD INTRODUCTION FEATURES AND TESTS EVALUATING THE AD8451 Test the Instrumentation Amplifier 20 mV Offset at IMEAS Output Test the Difference Amplifier 5 mV Offset at BVMEAS Output CC and CV Integrator Tests Loop Compensation SCHEMATIC AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE