Datasheet MIC4607 (Microchip) - 6
| 制造商 | Microchip |
| 描述 | 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection |
| 页数 / 页 | 42 / 6 — MIC4607. DC CHARACTERISTICS (Note 1, 2) (CONTINUED) |
| 修订版 | 08-23-2016 |
| 文件格式/大小 | PDF / 4.5 Mb |
| 文件语言 | 英语 |
MIC4607. DC CHARACTERISTICS (Note 1, 2) (CONTINUED)
文件文字版本
MIC4607
DC CHARACTERISTICS (Note 1, 2) (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VHS = 0V; No load on
xLO or xHO; TA = 25°C; unless noted. Bold values indicate –40°C< TJ < +125°C.
Parameters Sym. Min. Typ. Max. Units RD — 4 6 V — Low-Level Output Voltage VOLL — 0.3 0.6 V IxLO = 50 mA High-Level Output Voltage VOHL 0.5 1 V IxLO = 50 mA,
VOHL = VDD – VxLO Peak Sink Current IOHL — 1 — A VxLO = 0V Peak Source Current IOLL — 1 — A VxLO = 12V xHO Gate Driver
Low-Level Output Voltage VOLH — 0.3 0.6 V IxHO = 50 mA High-Level Output Voltage VOHH — 0.5 1 V IxHO = 50 mA,
VOHH = VxHB – VxHO Peak Sink Current IOHH — 1 — A VxHO = 0V Peak Source Current IOLH — 1 — A VxHO = 12V Dynamic Resistance Conditions xLO Gate Driver
— Switching Specifications (LI/HI mode with inputs non-overlapping, assumes HS low before LI goes high and
LO low before HI goes high).
Lower Turn-Off Propagation
Delay (LI Falling to LO Falling) tLPHL Upper Turn-Off Propagation
Delay (HI Falling to HO Falling) tHPHL Lower Turn-On Propagation
Delay (LI Rising to LO Rising) tLPLH Upper Turn-On Propagation
Delay (HI Rising to HO Rising) tHPLH —
—
—
— 35 75 ns — 35 75 ns — 35 75 ns — 35 75 ns — Output Rise/Fall Time tR/F — 20 — ns CL = 1000 pF Output Rise/Fall Time
(3V to 9V) tR/F — 0.8 — μs CL = 0.1 μF Minimum Input Pulse Width
that Changes the Output tPW — 50 — ns Note 4 Switching Specifications PWM Mode (MIC4607-2) or LI/HI mode (MIC4607-1) with Overlapping LI/HI Inputs
Delay from PWM Going High /
LI Low, to LO Going Low tLOOFF — 35 75 ns — LO Output Voltage Threshold
for LO FET to be Considered
Off VLOOFF — 1.9 — V — Delay from LO Off to HO Going
High tHOON — 35 75 ns — Delay from PWM or HI Going
Low to HO Going Low tHOOFF — 35 75 ns — Note 1:
2:
3: 4: “x” in front of a pin name refers to either A, B or C phase. (e.g. xHI can be either AHI, BHI or CHI).
Specification for packaged product only.
VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic
low.
VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic
high.
Guaranteed by design. Not production tested. DS20005610A-page 6 2016 Microchip Technology Inc.
DC CHARACTERISTICS (Note 1, 2) (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VHS = 0V; No load on
xLO or xHO; TA = 25°C; unless noted. Bold values indicate –40°C< TJ < +125°C.
Parameters Sym. Min. Typ. Max. Units RD — 4 6 V — Low-Level Output Voltage VOLL — 0.3 0.6 V IxLO = 50 mA High-Level Output Voltage VOHL 0.5 1 V IxLO = 50 mA,
VOHL = VDD – VxLO Peak Sink Current IOHL — 1 — A VxLO = 0V Peak Source Current IOLL — 1 — A VxLO = 12V xHO Gate Driver
Low-Level Output Voltage VOLH — 0.3 0.6 V IxHO = 50 mA High-Level Output Voltage VOHH — 0.5 1 V IxHO = 50 mA,
VOHH = VxHB – VxHO Peak Sink Current IOHH — 1 — A VxHO = 0V Peak Source Current IOLH — 1 — A VxHO = 12V Dynamic Resistance Conditions xLO Gate Driver
— Switching Specifications (LI/HI mode with inputs non-overlapping, assumes HS low before LI goes high and
LO low before HI goes high).
Lower Turn-Off Propagation
Delay (LI Falling to LO Falling) tLPHL Upper Turn-Off Propagation
Delay (HI Falling to HO Falling) tHPHL Lower Turn-On Propagation
Delay (LI Rising to LO Rising) tLPLH Upper Turn-On Propagation
Delay (HI Rising to HO Rising) tHPLH —
—
—
— 35 75 ns — 35 75 ns — 35 75 ns — 35 75 ns — Output Rise/Fall Time tR/F — 20 — ns CL = 1000 pF Output Rise/Fall Time
(3V to 9V) tR/F — 0.8 — μs CL = 0.1 μF Minimum Input Pulse Width
that Changes the Output tPW — 50 — ns Note 4 Switching Specifications PWM Mode (MIC4607-2) or LI/HI mode (MIC4607-1) with Overlapping LI/HI Inputs
Delay from PWM Going High /
LI Low, to LO Going Low tLOOFF — 35 75 ns — LO Output Voltage Threshold
for LO FET to be Considered
Off VLOOFF — 1.9 — V — Delay from LO Off to HO Going
High tHOON — 35 75 ns — Delay from PWM or HI Going
Low to HO Going Low tHOOFF — 35 75 ns — Note 1:
2:
3: 4: “x” in front of a pin name refers to either A, B or C phase. (e.g. xHI can be either AHI, BHI or CHI).
Specification for packaged product only.
VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic
low.
VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic
high.
Guaranteed by design. Not production tested. DS20005610A-page 6 2016 Microchip Technology Inc.