Datasheet KSZ8765CLX (Microchip) - 2

KSZ8765CLX
Option and Half-Duplex Back-Pressure Colli- • Power and Power Management sion Flow Control - Full-Chip Software Power-Down (All Register - IEEE 802.1w Rapid Spanning Tree Protocol Values are Not Saved and Strap-In value Will Support Re-Strap after it Releases the Power-Down) - IGMP v1/v2/v3 Snooping for Multicast Packet - Per-Port Software Power-Down Filtering - Energy Detect Power-Down (EDPD), which - QoS/CoS Packets Prioritization Support: Disables the PHY Transceiver When Cables 802.1p, DiffServ-Based and Re-Mapping of are Removed 802.1p Priority Field Per Port Basis on Four - Supports IEEE P802.3az Energy Efficient Priority Levels Ethernet (EEE) to Reduce Power Consump- - IPv4/IPv6 QoS Support tion in Transceivers in LPI State Even - IPV6 Multicast Listener Discovery (MLD) Though Cables are Not Removed Snooping - Dynamic Clock Tree Control to Reduce - Programmable Rate Limiting at the Ingress Clocking in Areas that are Not in Use and Egress Ports on a Per Port Basis - Low Power Consumption without Extra - Jitter-Free Per Packet Based Rate Limiting Power Consumption on Transformers Support - Voltages: Using External LDO Power Sup- - Tail Tag Mode (1 byte Added before FCS) plies Support on Port 5 to Inform the Processor - Analog VDDAT 3.3V or 2.5V which Ingress Port Receives the Packet - VDDIO Support 3.3V, 2.5V, and 1.8V - Broadcast Storm Protection with Percentage - Low 1.2V Voltage for Analog and Digital Core Control (Global and Per Port Basis) Power - 1K Entry Forwarding Table with 64 KB Frame - WoL Support with Configurable Packet Con- Buffer trol - 4 Priority Queues with Dynamic Packet Map- • Additional Features ping for IEEE 802.1P, IPV4 TOS (DIFF- - Single 25 MHz +50 ppm Reference Clock SERV), IPv6 Traffic Class, etc. Requirement - Supports WoL Using AMD’s Magic Packet - Comprehensive Programmable Two-LED - VLAN and Address Filtering Indicator Support for Link, Activity, Full-/Half- - Supports 802.1x Port-Based Security, Duplex, and 10/100 Speed Authentication and MAC-Based Authentica- • Packaging and Environmental tion via Access Control Lists (ACL) - Commercial Temperature Range: 0°C to - Provides Port-Based and Rule-Based ACLs +70°C to Support Layer 2 MAC SA/DA Address, - Industrial Temperature Range: –40°C to Layer 3 IP Address and IP Mask, Layer 4 +85°C TCP/UDP Port Number, IP Protocol, TCP Flag and Compensation for the Port Security - Package Available in an 80-Pin LQFP, Lead- Filtering Free (RoHS-Compliant) Package - Ingress and Egress Rate Limit Based on Bit - Supports Human Body Model (HBM) ESD per Second (bps) and Packet-Based Rate Rating of 5 kV Limiting (pps) - 0.065 µm CMOS Technology for Lower • Configuration Registers Access Power Consumption - High-Speed SPI (4-Wire, up to 50 MHz) Inter- face to Access All Internal Registers - MII Management (MIIM, MDC/MDIO 2-Wire) Interface to Access All PHY Registers per Clause 22.2.4.5 of the IEEE 802.3 Specifica- tion - I/O Pin Strapping Facility to Set Certain Reg- ister Bits from I/O Pins During Reset Time - Control Registers Configurable On-the-Fly  2016 Microchip Technology Inc. DS00002130A-page 2 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines