Datasheet LAN9312 (Microchip) - 9

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LAN9312
2.2.1 SYSTEM CLOCKS/RESET/PME CONTROLLER A clock module contained within the LAN9312 generates all the system clocks required by the device. This module inter- faces directly with the external 25MHz crystal/oscillator to generate the required clock divisions for each internal module, with the exception of the 1588 clocks, which are generated in the 1588 Time Stamp Clock/Events module. A 16-bit gen- eral purpose timer and 32-bit free-running clock are provided by this module for general purpose use. The LAN9312 reset events are categorized as chip-level resets, multi-module resets, and single-module resets. A chip-level reset is initiated by assertion of any of the following input events: • Power-On Reset • nRST Pin Reset A multi-module reset is initiated by assertion of the following: •
Digital Reset
- DIGITAL_RST (bit 0) in the Reset Control Register (RESET_CTL) - Resets all LAN9312 sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY) •
Soft Reset
- SRST (bit 0) in the Hardware Configuration Register (HW_CFG) - Resets the HBI, Host MAC, and System CSRs below address 100h A single-module reset is initiated by assertion of the following: •
Port 2 PHY Reset
- PHY2_RST (bit 2) in the Reset Control Register (RESET_CTL) or Reset (bit 15) in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) - Resets the Port 2 PHY •
Port 1 PHY Reset
- PHY1_RST (bit 1) in the Reset Control Register (RESET_CTL) or Reset (bit 15) in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) - Resets the Port 1 PHY •
Virtual PHY Reset
- VPHY_RST (bit 0) in the Reset Control Register (RESET_CTL), (bit 10) in the Power Man- agement Control Register (PMT_CTRL), or Reset (bit 15) in the Virtual PHY Basic Control Register (VPHY_BA- SIC_CTRL) - Resets the Virtual PHY The LAN9312 supports numerous power management and wakeup features. The Port 1 & 2 PHYs provide general power-down and energy detect power-down modes, which allow a reduction in PHY power consumption. The Host MAC provides wake-up frame detection and magic packet detection modes. The LAN9312 can be programmed to issue an external wake signal (PME) via several methods, including wake on LAN, wake on link status change (energy detect), and magic packet wakeup. The PME signal is ideal for triggering system power-up using remote Ethernet wakeup events. 2.2.2 SYSTEM INTERRUPT CONTROLLER The LAN9312 provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Con- troller. At the top level are the Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN). These reg- isters aggregate and control all interrupts from the various LAN9312 sub-modules. The LAN9312 is capable of generating interrupt events from the following: • 1588 Time Stamp • Switch Fabric • Ethernet PHYs • GPIOs • Host MAC (FIFOs, power management) • General Purpose Timer • Software (general purpose) A dedicated programmable IRQ interrupt output pin is provided for external indication of any LAN9312 interrupts. The IRQ pin is controlled via the Interrupt Configuration Register (IRQ_CFG), which allows configuration of the IRQ buffer type, polarity, and de-assertion interval.  2008-2016 Microchip Technology Inc. DS00002287A-page 9 Document Outline 1.0 Preface 1.1 General Terms 1.2 Buffer Types TABLE 1-1: Buffer Types 1.3 Register Nomenclature TABLE 1-2: Register Bit Types 2.0 Introduction 2.1 General Description 2.2 Block Diagram FIGURE 2-1: Internal LAN9312 Block Diagram 2.2.1 System Clocks/Reset/PME Controller 2.2.2 System Interrupt Controller 2.2.3 Switch Fabric 2.2.4 Ethernet PHYs 2.2.5 Host Bus Interface (HBI) 2.2.6 Host MAC 2.2.7 EEPROM Controller/Loader 2.2.8 1588 Time Stamp 2.2.9 GPIO/LED Controller 2.3 System Configuration FIGURE 2-2: System Block Diagram 3.0 Pin Description and Configuration 3.1 Pin Diagrams 3.1.1 128-VTQFP Pin Diagram FIGURE 3-1: LAN9312 128-VTQFP Pin Assignments (TOP VIEW) 3.1.2 128-XVTQFP Pin Diagram FIGURE 3-2: LAN9312 128-XVTQFP Pin Assignments (TOP VIEW) 3.2 Pin Descriptions TABLE 3-1: LAN Port 1 Pins TABLE 3-2: LAN Port 2 Pins TABLE 3-3: LAN Port 1 & 2 Power and Common Pins TABLE 3-4: Host Bus Interface Pins TABLE 3-5: EEPROM Pins TABLE 3-6: Dedicated Configuration Strap Pins TABLE 3-7: Miscellaneous Pins TABLE 3-8: PLL Pins TABLE 3-9: Core and I/O Power and Ground Pins TABLE 3-10: No-Connect Pins 4.0 Clocking, Resets, and Power Management 4.1 Clocks 4.2 Resets TABLE 4-1: Reset Sources and Affected LAN9312 Circuitry 4.2.1 Chip-Level Resets 4.2.2 Multi-Module Resets 4.2.3 Single-Module Resets 4.2.4 Configuration Straps TABLE 4-2: Soft-Strap Configuration Strap Definitions TABLE 4-3: Hard-Strap Configuration Strap Definitions 4.3 Power Management FIGURE 4-1: PME and PME_INT Signal Generation 4.3.1 Port 1 & 2 PHY Power Management 4.3.2 Host MAC Power Management 5.0 System Interrupts 5.1 Functional Overview 5.2 Interrupt Sources FIGURE 5-1: Functional Interrupt Register Hierarchy 5.2.1 1588 Time Stamp Interrupts 5.2.2 Switch Fabric Interrupts 5.2.3 Ethernet PHY Interrupts 5.2.4 GPIO Interrupts 5.2.5 Host MAC Interrupts 5.2.6 Power Management Interrupts 5.2.7 General Purpose Timer Interrupt 5.2.8 Software Interrupt 5.2.9 Device Ready Interrupt 6.0 Switch Fabric 6.1 Functional Overview 6.2 Switch Fabric CSRs 6.2.1 Switch Fabric CSR Writes FIGURE 6-1: Switch Fabric CSR Write Access Flow Diagram 6.2.2 Switch Fabric CSR Reads FIGURE 6-2: Switch Fabric CSR Read Access Flow Diagram 6.2.3 Flow Control Enable Logic TABLE 6-1: Switch Fabric Flow Control Enable Logic 6.3 10/100 Ethernet MACs 6.3.1 Receive MAC 6.3.2 Transmit MAC 6.4 Switch Engine (SWE) 6.4.1 MAC Address Lookup Table FIGURE 6-3: ALR Table Entry Structure 6.4.2 Forwarding Rules 6.4.3 Transmit Priority Queue Selection FIGURE 6-4: Switch Engine Transmit Queue Selection FIGURE 6-5: Switch Engine Transmit Queue Calculation 6.4.4 VLAN Support TABLE 6-2: VLAN Table Entry Structure 6.4.5 Spanning Tree Support TABLE 6-3: Spanning Tree States 6.4.6 Ingress Flow Metering and Coloring TABLE 6-4: Typical Ingress Rate Settings FIGURE 6-6: Switch Engine Ingress Flow Priority Selection FIGURE 6-7: Switch Engine Ingress Flow Priority Calculation 6.4.7 Broadcast Storm Control TABLE 6-5: Typical Broadcast Rate Settings 6.4.8 IPv4 IGMP Support 6.4.9 Port Mirroring 6.4.10 Host CPU Port Special Tagging 6.4.11 Counters 6.5 Buffer Manager (BM) 6.5.1 Packet Buffer Allocation 6.5.2 Random Early Discard (RED) 6.5.3 Transmit Queues 6.5.4 Transmit Priority Queue Servicing 6.5.5 Egress Rate Limiting (Leaky Bucket) TABLE 6-6: Typical Egress Rate Settings 6.5.6 Adding, Removing, and Changing VLAN Tags FIGURE 6-8: Hybrid Port Tagging and Un-tagging 6.5.7 Counters 6.6 Switch Fabric Interrupts 7.0 Ethernet PHYs 7.1 Functional Overview 7.1.1 PHY Addressing TABLE 7-1: Default PHY Serial MII Addressing 7.2 Port 1 & 2 PHYs FIGURE 7-1: Port x PHY Block Diagram 7.2.1 100BASE-TX Transmit FIGURE 7-2: 100BASE-TX Transmit Data Path TABLE 7-2: 4B/5B Code Table 7.2.2 100BASE-TX Receive FIGURE 7-3: 100BASE-TX Receive Data Path 7.2.3 10BASE-T Transmit 7.2.4 10BASE-T Receive 7.2.5 PHY Auto-negotiation 7.2.6 HP Auto-MDIX FIGURE 7-4: Direct Cable Connection vs. Cross-Over Cable Connection 7.2.7 MII MAC Interface 7.2.8 PHY Management Control TABLE 7-3: PHY Interrupt Sources 7.2.9 PHY Power-Down Modes 7.2.10 PHY Resets 7.2.11 LEDs 7.2.12 Required Ethernet Magnetics 7.3 Virtual PHY 7.3.1 Virtual PHY Auto-Negotiation 7.3.2 Virtual PHY Resets 8.0 Host Bus Interface (HBI) 8.1 Functional Overview 8.2 Host Memory Mapping 8.3 Host Endianess FIGURE 8-1: Little Endian Byte Ordering FIGURE 8-2: Big Endian Byte Ordering 8.4 Host Interface Timing 8.4.1 Special Situations 8.4.2 Special Restrictions on Back-to Back Write-Read Cycles TABLE 8-1: Read After Write Timing Rules 8.4.3 Special Restrictions on Back-to-Back Read Cycles TABLE 8-2: Read After Read Timing Rules 8.4.4 PIO Reads FIGURE 8-3: Functional Timing for PIO Read Operation 8.4.5 PIO Burst Reads FIGURE 8-4: Functional Timing for PIO Burst Read Operation 8.4.6 RX Data FIFO Direct PIO Reads FIGURE 8-5: Functional Timing for RX Data FIFO Direct PIO Read Operation 8.4.7 RX Data FIFO Direct PIO Burst Reads FIGURE 8-6: Functional Timing for RX Data FIFO Direct PIO Burst Read Operation 8.4.8 PIO Writes FIGURE 8-7: Functional Timing for PIO Write Operation 8.4.9 TX Data FIFO Direct PIO Writes FIGURE 8-8: Functional Timing for TX Data FIFO Direct PIO Write Operation 8.5 HBI Interrupts 9.0 Host MAC 9.1 Functional Overview 9.2 Flow Control 9.2.1 Full-Duplex Flow Control 9.2.2 Half-Duplex Flow Control (Backpressure) 9.3 Virtual Local Area Network (VLAN) Support FIGURE 9-1: VLAN Frame 9.4 Address Filtering TABLE 9-1: Address Filtering Modes 9.4.1 Perfect Filtering 9.4.2 Hash Only Filtering 9.4.3 Hash Perfect Filtering 9.4.4 Inverse Filtering 9.5 Wake-up Frame Detection TABLE 9-2: Wake-Up Frame Filter Register Structure TABLE 9-3: Filter i Byte Mask Bit Definitions TABLE 9-4: Filter i Command Bit Definitions TABLE 9-5: Filter i Offset Bit Definitions TABLE 9-6: Filter i CRC-16 Bit Definitions 9.5.1 Magic Packet Detection 9.6 Host MAC Address TABLE 9-7: EEPROM Byte Ordering and Register Correlation FIGURE 9-2: Example EEPROM MAC Address Setup 9.7 FIFOs 9.7.1 TX/RX FIFOs 9.7.2 MIL FIFOs 9.7.3 FIFO Memory Allocation Configuration TABLE 9-8: TX/RX FIFO Configurable Sizes TABLE 9-9: Valid TX/RX FIFO Allocations 9.8 TX Data Path Operation FIGURE 9-3: Simplified Host TX Flow Diagram 9.8.1 TX Buffer Format FIGURE 9-4: TX Buffer Format 9.8.2 TX Command Format TABLE 9-10: TX Command 'A' Format TABLE 9-11: TX Command 'B' Format 9.8.3 TX Data Format TABLE 9-12: TX DATA Start Offset 9.8.4 TX Status Format 9.8.5 Calculating Actual TX Data FIFO Usage 9.8.6 Transmit Examples FIGURE 9-5: TX Example 1 FIGURE 9-6: TX Example 2 9.8.7 Transmitter Errors 9.8.8 Stopping and Starting the Transmitter 9.9 RX Data Path Operation 9.9.1 RX Slave PIO Operation FIGURE 9-7: Host Receive Routine Using Interrupts FIGURE 9-8: Host Receive Routine Using Polling 9.9.2 RX Packet Format FIGURE 9-9: RX Packet Format 9.9.3 RX Status Format 9.9.4 Stopping and Starting the Receiver 9.9.5 Receiver Errors 10.0 Serial Management 10.1 Functional Overview 10.2 I2C/Microwire Master EEPROM Controller TABLE 10-1: I2C/Microwire Master Serial Management Pins Characteristics 10.2.1 EEPROM Controller Operation FIGURE 10-1: EEPROM Access Flow Diagram 10.2.2 I2C EEPROM TABLE 10-2: I2C EEPROM Size Ranges FIGURE 10-2: I2C Cycle FIGURE 10-3: I2C EEPROM Addressing FIGURE 10-4: I2C EEPROM Byte Read FIGURE 10-5: I2C EEPROM Sequential Byte Reads FIGURE 10-6: I2C EEPROM Byte Write 10.2.3 Microwire EEPROM TABLE 10-3: Microwire EEPROM Size Ranges TABLE 10-4: Microwire Command Set for 7 Address Bits TABLE 10-5: Microwire Command Set for 9 Address Bits TABLE 10-6: Microwire Command Set for 11 Address Bits FIGURE 10-7: EEPROM ERASE Cycle FIGURE 10-8: EEPROM ERAL Cycle FIGURE 10-9: EEPROM EWDS Cycle FIGURE 10-10: EEPROM EWEN Cycle FIGURE 10-11: EEPROM READ Cycle FIGURE 10-12: EEPROM WRITE Cycle FIGURE 10-13: EEPROM WRAL Cycle 10.2.4 EEPROM Loader TABLE 10-7: EEPROM Contents Format Overview FIGURE 10-14: EEPROM Loader Flow Diagram TABLE 10-8: EEPROM Configuration Bits 11.0 IEEE 1588 Hardware Time Stamp Unit 11.1 Functional Overview 11.1.1 IEEE 1588 11.1.2 Block Diagram FIGURE 11-1: IEEE 1588 Block Diagram 11.2 IEEE 1588 Time Stamp TABLE 11-1: IEEE 1588 Message Type Detection FIGURE 11-2: IEEE 1588 Message Time Stamp Point TABLE 11-2: Time Stamp Capture Delay 11.2.1 Capture Locking 11.2.2 PTP Message Detection TABLE 11-3: PTP Multicast Addresses 11.3 IEEE 1588 Clock TABLE 11-4: Typical IEEE 1588 Clock Addend Values 11.4 IEEE 1588 Clock/Events 11.5 IEEE 1588 GPIOs 11.6 IEEE 1588 Interrupts 12.0 General Purpose Timer & Free-Running Clock 12.1 General Purpose Timer 12.2 Free-Running Clock 13.0 GPIO/LED Controller 13.1 Functional Overview 13.2 GPIO Operation 13.2.1 GPIO IEEE 1588 Timestamping 13.2.2 GPIO Interrupts 13.3 LED Operation TABLE 13-1: LED Operation as a Function of LED_CFG[9:8] 14.0 Register Descriptions FIGURE 14-1: LAN9312 Base Register Memory Map 14.1 TX/RX FIFO Ports 14.1.1 TX/RX Data FIFO’s 14.1.2 TX/RX Status FIFO’s 14.1.3 Direct FIFO Access Mode 14.2 System Control and Status Registers TABLE 14-1: System Control and Status Registers 14.2.1 Interrupts 14.2.2 Host MAC & FIFO’s TABLE 14-2: Backpressure Duration Bit Mapping 14.2.3 GPIO/LED 14.2.4 EEPROM 14.2.5 IEEE 1588 14.2.6 Switch Fabric TABLE 14-3: Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map 14.2.7 PHY Management Interface (PMI) 14.2.8 Virtual PHY TABLE 14-4: Virtual PHY MII Serially Adressable Register Index TABLE 14-5: Emulated Link Partner Pause Flow Control Ability Default Values 14.2.9 Miscellaneous 14.3 Host MAC Control and Status Registers TABLE 14-6: Host MAC Adressable Registers 14.3.1 Host MAC Control Register (HMAC_CR) 14.3.2 Host MAC Address High Register (HMAC_ADDRH) 14.3.3 Host MAC Address Low Register (HMAC_ADDRL) 14.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH) 14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL) 14.3.6 Host MAC MII Access Register (HMAC_MII_ACC) 14.3.7 Host MAC MII Data Register (HMAC_MII_DATA) 14.3.8 Host MAC Flow Control Register (HMAC_FLOW) 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1) 14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2) 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF) 14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR) 14.4 Ethernet PHY Control and Status Registers 14.4.1 Virtual PHY Registers 14.4.2 Port 1 & 2 PHY Registers TABLE 14-7: Port 1 & 2 PHY MII Serially Adressable Registers TABLE 14-8: 10BASE-T Full Duplex Advertisement Default Value TABLE 14-9: 10BASE-T Half Duplex Advertisement Bit Default Value TABLE 14-10: MODE[2:0] Definitions TABLE 14-11: Auto-MDIX Enable and Auto-MDIX State Bit Functionality 14.5 Switch Fabric Control and Status Registers TABLE 14-12: Indirectly Accessible Switch Control and Status Registers 14.5.1 General Switch CSRs 14.5.2 Switch Port 0, Port 1, and Port 2 CSRs 14.5.3 Switch Engine CSRs TABLE 14-13: Metering/Color Table Register Descriptions 14.5.4 Buffer Manager CSRs 15.0 Operational Characteristics 15.1 Absolute Maximum Ratings* 15.2 Operating Conditions** 15.3 Power Consumption TABLE 15-1: Supply and Current (10BASE-T Full-Duplex) TABLE 15-2: Supply and Current (100BASE-TX Full-Duplex) 15.4 DC Specifications TABLE 15-3: I/O Buffer Characteristics TABLE 15-4: 100BASE-TX Transceiver Characteristics TABLE 15-5: 10BASE-T Transceiver Characteristics 15.5 AC Specifications 15.5.1 Equivalent Test Load FIGURE 15-1: Output Equivalent Test Load 15.5.2 Reset and Configuration Strap Timing FIGURE 15-2: nRST Reset Pin Timing TABLE 15-6: nRST Reset Pin Timing Values 15.5.3 Power-On Configuration Strap Valid Timing FIGURE 15-3: Power-On Configuration Strap Latching Timing TABLE 15-7: Power-On Configuration Strap Latching Timing Values 15.5.4 PIO Read Cycle Timing FIGURE 15-4: PIO Read Cycle Timing TABLE 15-8: PIO Read Cycle Timing Values 15.5.5 PIO Burst Read Cycle Timing FIGURE 15-5: PIO Burst Read Cycle Timing TABLE 15-9: PIO Burst Read Cycle Timing Values 15.5.6 RX Data FIFO Direct PIO Read Cycle Timing FIGURE 15-6: RX Data FIFO Direct PIO Read Cycle Timing TABLE 15-10: RX Data FIFO Direct PIO Read Cycle Timing Values 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing FIGURE 15-7: RX Data FIFO Direct PIO Burst Read Cycle Timing TABLE 15-11: RX Data FIFO Direct PIO Burst Read Cycle Timing Values 15.5.8 PIO Write Cycle Timing FIGURE 15-8: PIO Write Cycle Timing TABLE 15-12: PIO Write Cycle Timing Values 15.5.9 TX Data FIFO Direct PIO Write Cycle Timing FIGURE 15-9: TX Data FIFO Direct PIO Write Cycle Timing TABLE 15-13: TX Data FIFO Direct PIO Write Cycle Timing Values 15.5.10 Microwire Timing FIGURE 15-10: Microwire Timing TABLE 15-14: Microwire Timing Values 15.6 Clock Circuit TABLE 15-15: LAN9312Crystal Specifications 16.0 Package Outlines 16.1 128-VTQFP Package Outline FIGURE 16-1: 128-vTQFP, 14x14x1.0mm body, 0.4mm Pitch FIGURE 16-2: 128-VTQFP Recommended PCB Land Pattern 16.2 128-XVTQFP Package Outline FIGURE 16-3: 128-XVTQFP 14x14x1.0mm Body, 0.4mm Pitch Appendix A: Data sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service