Datasheet LAN9354 (Microchip) - 8

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LAN9354 2.0 GENERAL DESCRIPTION
The LAN9354 is a full featured, 3 port 10/100 managed Ethernet switch designed for embedded applications where per- formance, flexibility, ease of integration and system cost control are required. The LAN9354 combines all the functions of a 10/100 switch system, including the Switch Fabric, packet buffers, Buffer Manager, Media Access Controllers (MACs), PHY transceivers, and serial management. IEEE 1588v2 is supported via the integrated IEEE 1588v2 hard- ware time stamp unit, which supports end-to-end and peer-to-peer transparent clocks. The LAN9354 complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet (EEE) (100Mbps only), and 802.1D/802.1Q network management protocol specifications, enabling compatibility with industry standard Ethernet and Fast Ethernet applications. 100BASE-FX is supported via an external fiber transceiver. At the core of the device is the high performance, high efficiency 3 port Ethernet Switch Fabric. The Switch Fabric con- tains a 3 port VLAN layer 2 Switch Engine that supports untagged, VLAN tagged, and priority tagged frames. The Switch Fabric provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed, and a 512 entry forwarding table provides ample room for MAC address forward- ing tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the Buffer Manager block within the Switch Fabric. All aspects of the Switch Fabric are managed via the Switch Fabric configuration and status registers, which are indirectly accessible via the system control and status registers. The LAN9354 provides 3 switched ports. Each port is fully compliant with the IEEE 802.3 standard and all internal MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The LAN9354 provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the third MAC are used to connect the Switch Fabric to an external MAC or PHY. In MAC mode, the device can be connected to an external PHY via the RMII interface. In PHY mode, the device can be connected to an external MAC via the RMII interface. All ports support automatic or manual full duplex flow con- trol or half duplex backpressure (forced collision) flow control. 2K jumbo packet (2048 byte) support allows for oversized packet transfers, effectively increasing throughput while decreasing CPU load. All MAC and PHY related settings are fully configurable via their respective registers within the device. The integrated I2C and SMI slave controllers allow for full serial management of the device via the integrated I2C or RMII interface, respectively. The inclusion of these interfaces allows for greater flexibility in the incorporation of the device into various designs. It is this flexibility which allows the device to operate in 2 different modes and under various man- agement conditions. In both MAC and PHY modes, the device can be SMI managed or I2C managed. This flexibility in management makes the LAN9354 a candidate for virtually all switch applications. The LAN9354 supports numerous power management and wakeup features. The LAN9354 can be placed in a reduced power mode and can be programmed to issue an external wake signal (IRQ) via several methods, including “Magic Packet”, “Wake on LAN”, wake on broadcast, wake on perfect DA, and “Link Status Change”. This signal is ideal for triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power state via a host processor command or one of the wake events. The LAN9354 contains an I2C master EEPROM controller for connection to an optional EEPROM. This allows for the storage and retrieval of static data. The internal EEPROM Loader can be optionally configured to automatically load stored configuration settings from the EEPROM into the device at reset. The I2C management slave and master EEPROM controller share common pins. In addition to the primary functionality described above, the LAN9354 provides additional features designed for extended functionality. These include a configurable 16-bit General Purpose Timer (GPT), a 32-bit 25MHz free running counter, a configurable GPIO/LED interface, and IEEE 1588 time stamping on all ports and all GPIOs. The IEEE time stamp unit provides a 64-bit tunable clock for accurate PTP timing and a timer comparator to allow time based interrupt generation. The LAN9354 can be configured to operate via a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system power dissipation. The LAN9354 is available in commercial and industrial temperature ranges. Figure 2-1 provides an internal block dia- gram of the LAN9354. DS00001926B-page 8  2015 Microchip Technology Inc. Document Outline Highlights Target Applications Key Benefits 1.0 Preface TABLE 1-1: General Terms (Continued) TABLE 1-2: Buffer Types TABLE 1-3: Register Nomenclature 2.0 General Description FIGURE 2-1: Internal Block Diagram 3.0 Pin Descriptions and Configuration FIGURE 3-1: 56-QFN Pin Assignments (Top View) TABLE 3-1: 56-QFN Package Pin Assignments (Continued) TABLE 3-2: LAN Port A Pin Descriptions (Continued) TABLE 3-3: LAN Port B Pin Descriptions (Continued) TABLE 3-4: LAN Port A & B Power and Common Pin Descriptions TABLE 3-5: Switch Port 0 RMII & Configuration Strap Pin Descriptions (Continued) TABLE 3-6: I2C Management Pin Descriptions TABLE 3-7: EEPROM Pin Descriptions TABLE 3-8: GPIO, LED & Configuration Strap Pin Descriptions (Continued) TABLE 3-9: Miscellaneous Pin Descriptions (Continued) TABLE 3-10: JTAG Pin Descriptions TABLE 3-11: Core and I/O Power Pin Descriptions 4.0 Power Connections FIGURE 4-1: Power Connections - Regulators Enabled FIGURE 4-2: Power Connections - Regulators Disabled 5.0 Register Map FIGURE 5-1: Register Address Map TABLE 5-1: System Control and Status Registers (Continued) TABLE 5-2: Read After Write Timing Rules (Continued) TABLE 5-3: Read After Read Timing Rules 6.0 Clocks, Resets, and Power Management TABLE 6-1: Reset Sources and Affected Device Functionality (Continued) FIGURE 6-1: PME Interrupt Signal Generation TABLE 6-2: Power Management States 7.0 Configuration Straps TABLE 7-1: Soft-Strap Configuration Strap Definitions (Continued) TABLE 7-2: Hard-Strap Configuration Strap Definitions (Continued) TABLE 7-3: Port 0 Mode Strap Mapping 8.0 System Interrupts FIGURE 8-1: Functional Interrupt Hierarchy TABLE 8-1: Interrupt Registers 9.0 Ethernet PHYs TABLE 9-1: Default PHY Serial MII Addressing FIGURE 9-1: Physical PHY Block Diagram FIGURE 9-2: 100BASE-TX Transmit Data Path TABLE 9-2: 4B/5B Code Table (Continued) FIGURE 9-3: 100BASE-TX Receive Data Path FIGURE 9-4: Direct Cable Connection vs. Cross-Over Cable Connection TABLE 9-3: Interrupt Management Table (Continued) TABLE 9-4: Alternative Interrupt Mode Management Table TABLE 9-5: Wakeup Generation Cases FIGURE 9-5: TDR Usage Flow Diagram TABLE 9-6: TDR Propagation Constants TABLE 9-7: Typical Measurement Error for Open Cable (+/- Meters) (Continued) TABLE 9-8: Typical Measurement Error for Shorted Cable (+/- Meters) TABLE 9-9: Match Case Estimated Cable Length (CBLN) Lookup (Continued) FIGURE 9-6: Near-end Loopback Block Diagram FIGURE 9-7: Connection Loopback Block Diagram TABLE 9-10: 100BASE-FX LOS, SD and TP Copper Selection PHY A TABLE 9-11: 100BASE-FX LOS, SD and TP Copper Selection PHY B FIGURE 9-8: Physical PHY External Access Timing TABLE 9-12: Physical PHY External Access Timing Values TABLE 9-13: Physical PHY A and B MII Serially Accessible Control and Status Registers (Continued) TABLE 9-14: 10BASE-T Full Duplex Advertisement Default Value TABLE 9-15: 10BASE-T Half Duplex Advertisement Bit Default Value TABLE 9-16: MODE[2:0] Definitions (Continued) TABLE 9-17: Auto-MDIX Enable and Auto-MDIX State Bit Functionality TABLE 9-18: MDIX Strap Functionality TABLE 9-19: MMD Registers (Continued) FIGURE 9-9: Virtual PHY Timing TABLE 9-20: Virtual PHY Timing Values TABLE 9-21: Virtual PHY MII Serially Addressable Register Index TABLE 9-22: Emulated Link Partner Pause Flow Control Ability Default Values TABLE 9-23: Emulated Link Partner Default Advertised Ability 10.0 Switch Fabric FIGURE 10-1: ALR Table Entry Structure FIGURE 10-2: Switch Engine Transmit Queue Selection FIGURE 10-3: Switch Engine Transmit Queue Calculation FIGURE 10-4: VLAN Table Entry Structure TABLE 10-1: Spanning Tree States (Continued) TABLE 10-2: Typical Ingress Rate Settings FIGURE 10-5: Switch Engine Ingress Flow Priority Selection FIGURE 10-6: Switch Engine Ingress Flow Priority Calculation TABLE 10-3: Typical Broadcast Rate Settings TABLE 10-4: Typical Egress Rate Settings FIGURE 10-7: Hybrid Port Tagging and Un-Tagging TABLE 10-5: Switch Fabric Flow Control Enable Logic FIGURE 10-8: Switch Fabrics CSR Write Access Flow Diagram FIGURE 10-9: Switch Fabrics CSR Read Access Flow Diagram TABLE 10-6: Switch Fabric Interface Logic Registers TABLE 10-7: SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH and EEPROM Byte Ordering FIGURE 10-10: Example SWITCH_MAC_ADDL, SWITCH_MAC_ADDRH and EEPROM Setup TABLE 10-8: Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map (Continued) (Continued) TABLE 10-9: Indirectly Accessible Switch Control and Status Registers (Continued) TABLE 10-10: Metering/Color Table Register Descriptions 11.0 I2C Slave Controller 11.1 Functional Overview 11.2 I2C Overview 11.3 I2C Slave Operation 11.3.1 I2C Slave Command Format 11.3.2 Device Initialization 11.3.2.1 I2C Slave Read Polling for Initialization Complete 11.3.3 Access During and Following Power Management 11.3.4 I2C Slave Read Sequence 11.3.5 I2C Slave Write Sequence 12.0 I2C Master EEPROM Controller FIGURE 12-1: I2C Cycle FIGURE 12-2: I2C Master Timing TABLE 12-1: I2C Master Timing Values (Continued) TABLE 12-2: I2C EEPROM Size Ranges FIGURE 12-3: I2C EEPROM Addressing FIGURE 12-4: I2C EEPROM Byte Read FIGURE 12-5: I2C EEPROM Sequential Byte Reads FIGURE 12-6: I2C EEPROM Byte Write FIGURE 12-7: EEPROM Access Flow Diagram TABLE 12-3: EEPROM Contents Format Overview FIGURE 12-8: EEPROM Loader Flow Diagram TABLE 12-4: EEPROM Configuration Bits TABLE 12-5: I2C Master EEPROM Controller Registers 13.0 MII Data Interfaces 13.1 Port 0 Data Path 13.1.1 Port 0 RMII MAC Mode 13.1.1.1 Reference Clock Selection 13.1.1.2 Clock Drive Strength 13.1.2 Port 0 RMII PHY Mode 13.1.2.1 Isolate 13.1.2.2 Reference Clock Selection 13.1.2.3 Clock Drive Strength 13.1.2.4 Collision Test 13.1.2.5 Loopback Mode 13.2 Port 1 Data Path 13.2.1 Port 1 Internal PHY Mode 13.3 Port 2 Data Path 13.3.1 Port 2 Internal PHY Mode 13.4 Switch Fabric Timing Requirements 13.4.1 RMII Interface Timing (MAC Mode) 13.4.2 RMII Interface Timing (PHY Mode) 14.0 MII Management 14.1 Functional Overview 14.2 SMI Slave Controller 14.2.1 Device Initialization 14.2.2 Access During and Following Power Management 14.2.3 SMI Slave Command Format 14.2.3.1 Read Sequence 14.2.3.2 Write Sequence 14.2.4 SMI Timing Requirements 14.3 PHY Management Interface (PMI) 14.3.1 PMI Slave Command Format 14.3.2 PHY Register Host Access 14.3.3 EEPROM Loader PHY Register Access 14.3.4 PMI Timing Requirements 14.3.5 PHY Management Interface (PMI) Registers 14.3.5.1 PHY Management Interface Data Register (PMI_DATA) 14.3.5.2 PHY Management Interface Access Register (PMI_ACCESS) 14.4 MII Management Multiplexer 14.4.1 Port 0 Management Path Configurations 14.4.1.1 Port 0 MAC Mode SMI Managed 14.4.1.2 Port 0 MAC Mode SMI Managed - Device Initialization 14.4.1.3 Port 0 PHY Mode SMI Managed 14.4.1.4 Port 0 PHY Mode SMI Managed - Device Initialization 14.4.1.5 Port 0 MAC Mode I2C Managed 14.4.1.6 Port 0 PHY Mode I2C Managed 15.0 IEEE 1588 FIGURE 15-1: 1588 Clock Block Diagram FIGURE 15-2: 1588 Clock Event Block Diagram TABLE 15-1: 1588 Control and Status Registers (Continued) 16.0 General Purpose Timer & Free-Running Clock TABLE 16-1: Miscellaneous Registers 17.0 GPIO/LED Controller TABLE 17-1: LED Operation as a Function of LED_FUN[2:0] = 000b - 011b TABLE 17-2: LED Operation as a Function of LED_FUN[2:0] = 100b - 111b TABLE 17-3: GPIO/LED Registers 18.0 Miscellaneous TABLE 18-1: Miscellaneous Registers 19.0 JTAG TABLE 19-1: IEEE 1149.1 Op Codes FIGURE 19-1: JTAG Timing TABLE 19-2: JTAG Timing Values 20.0 Operational Characteristics TABLE 20-1: 56-PIN QFN Package Thermal Parameters TABLE 20-2: Maximum Power Dissipation TABLE 20-3: Current Consumption and Power Dissipation (Regs. Disabled) (Continued) TABLE 20-4: Current Consumption and Power Dissipation (Regs. Enabled) (Continued) TABLE 20-5: Non-Variable I/O DC Electrical Characteristics (Continued) TABLE 20-6: Variable I/O DC Electrical Characteristics TABLE 20-7: 100BASE-TX Transceiver Characteristics TABLE 20-8: 10BASE-T Transceiver Characteristics FIGURE 20-1: Output Equivalent Test Load FIGURE 20-2: Power Sequence Timing - Internal Regulators FIGURE 20-3: Power Sequence Timing - External Regulators TABLE 20-9: Power Sequencing Timing Values FIGURE 20-4: RST# Pin Configuration Strap Latching Timing TABLE 20-10: RST# Pin Configuration Strap Latching Timing Values FIGURE 20-5: Power-On Configuration Strap Latching Timing TABLE 20-11: Power-On Configuration Strap Latching Timing Values TABLE 20-12: Crystal Specifications 21.0 Package Outlines FIGURE 21-1: 56-QFN Package FIGURE 21-2: 56-QFN Package Dimensions 22.0 Revision History TABLE 22-1: Revision History The Microchip Web Site Product Identification System Worldwide Sales and Service