Datasheet LTC1863L, LTC1867L (Analog Devices) - 9

LTC1863L/LTC1867L
APPLICATIONS INFORMATION Overview Examples of Multiplexer Options 4 Differential 8 Single-Ended
The LTC1863L/LTC1867L are complete, low power, multi- + (–) CH0 + CH0 plexed ADCs. They consist of a 12-/16-bit, 175ksps capac- – { (+) CH1 + CH1 + CH2 itive successive approximation A/D converter, a precision + (–) CH2 + CH3 – { (+) CH3 + CH4 internal reference, a configurable 8-channel analog input + CH5 + (–){ CH4 multiplexer (MUX) and a serial port for data transfer. + CH6 – (+) CH5 + CH7/COM + (–){ CH6 Conversions are started by a rising edge on the CS/CONV – (+) CH7/COM GND (–) input. Once a conversion cycle has begun, it cannot be
7 Single-Ended Combinations of Differential
restarted. Between conversions, the ADCs receive an
to CH7/COM and Single-Ended
input word for channel selection and output the conver- + CH0 + CH0 + { CH1 – CH1 sion result, and the analog input is acquired in preparation + CH2 + CH3 – CH2 +{ for the next conversion. In the acquire phase, a minimum + CH4 CH3 + CH5 + CH4 time of 2.01µs will provide enough time for the sample- + CH6 + CH5 + CH6 and-hold capacitors to acquire the analog signal. + CH7/COM CH7/COM (–) GND (–) 1863L7L AI01 During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from
Changing the MUX Assignment “On the Fly” 1st Conversion 2nd Conversion
the most significant bit (MSB) to the least significant bit (LSB). The input is sucessively compared with the binary + CH2 – CH2 – { CH3 + { CH3 weighted charges supplied by the differential capacitive + CH4 + { CH4 CH5 + { DAC. Bit decisions are made by a low power, differen- – CH5 CH7/COM CH7/COM (–) tial comparator that rejects common mode noise. At the (UNUSED) 1863L7L AI02 end of a conversion, the DAC output balances the ana- Tables 1 and 2 show the configurations when COM = 0, log input. The SAR content (a 12-/16-bit data word) that and COM = 1. represents the analog input is loaded into the 12-/16-bit output latches.Analog Input Multiplexer
Table 1. Channel Configuration (When COM = 0, CH7/COM Pin Is Used as CH7)
The analog input multiplexer is controlled by a 7-bit input
Channel Configuration
data word. The input data word is defined as follows:
SD OS S1 S0 COM “+” “–”
0 0 0 0 0 CH0 CH1 SD OS S1 S0 COM UNI SLP 0 0 0 1 0 CH2 CH3 SD = SINGLE/DIFFERENTIAL BIT 0 0 1 0 0 CH4 CH5 0 0 1 1 0 CH6 CH7 OS = ODD/SIGN BIT 0 1 0 0 0 CH1 CH0 S1 = ADDRESS SELECT BIT 1 0 1 0 1 0 CH3 CH2 0 1 1 0 0 CH5 CH4 S0 = ADDRESS SELECT BIT 0 0 1 1 1 0 CH7 CH6 COM = CH7/COM CONFIGURATION BIT 1 0 0 0 0 CH0 GND UNI = UNIPOLAR/BIPOLAR BIT 1 0 0 1 0 CH2 GND 1 0 1 0 0 CH4 GND SLP = SLEEP MODE BIT 1 0 1 1 0 CH6 GND 1 1 0 0 0 CH1 GND 1 1 0 1 0 CH3 GND 1 1 1 0 0 CH5 GND 1 1 1 1 0 CH7 GND 1863l7lfe For more information www.linear.com/LTC1863L 9 Document Outline Description Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Package Description Related Parts