Datasheet AD5748 (Analog Devices) - 10

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AD5748 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P T T M C L E E U T/ L A T T E FI L E S / U S C A E W C C C C N F R H N N N N 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 SDO/VFAULT 1 24 VSENSE+ CLRSEL 2 23 VOUT CLEAR 3 22 VSENSE– AD5748 DV 4 21 AV CC SS GND 5 TOP VIEW 20 COMP1 (Not to Scale) SYNC/RSET 6 19 COMP2 SCLK/OUTEN 7 18 IOUT SDIN/R0 8 17 AVDD 9 0 1 2 3 4 5 6 1 1 1 1 1 1 1 1 2 3 2 1 F N D R E I / R/ R/ T T V N 2 1 0 X X RV G D D D E E A A A R R
4
NOTES
-00
1. NC = NO CONNECT.
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2. THE EXPOSED PADDLE IS TIED TO AVSS.
089 Figure 4. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 SDO/VFAULT Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin is a CMOS output. Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. 2 CLRSEL In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software mode, this pin is implemented as a logic OR with the internal CLRSEL bit. 3 CLEAR Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the range selected (user-selectable). CLEAR is a logic OR with the internal clear bit. In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details. 4 DVCC Digital Power Supply. 5 GND Ground Connection. 6 SYNC/RSET Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data into the AD5748, also updating the output. Resistor Select (RSET). In hardware mode, this pin chooses whether the internal or the external current sense resistor is used. If RSET = 0, the external sense resistor is chosen. If RSET = 1, the internal sense resistor is chosen. 7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds of up to 50 MHz. Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin. 8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK. Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output current/voltage range setting on the part. 9 AD2/R1 Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight devices to be addressed on one bus. Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output current/voltage range setting on the part. 10 AD1/R2 Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0 allows up to eight devices to be addressed on one bus. Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output current/voltage range setting on the part. Rev. B | Page 10 of 32 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Terminology Theory of Operation Software Mode Current Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of the AD5748 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Readback Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) Current Setting Resistor Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide