Preliminary Datasheet ADAR1000 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 4 Channel X/Ku Band Beamformer |
| 页数 / 页 | 51 / 6 — ADAR1000. Preliminary Technical Data. TIMING SPECIFICATIONS. Table 2. SPI … |
| 修订版 | PrF |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
ADAR1000. Preliminary Technical Data. TIMING SPECIFICATIONS. Table 2. SPI Timing. Parameter. Min. Typ. Max. Unit. Condition. Timing Diagram
文件文字版本
ADAR1000 Preliminary Technical Data TIMING SPECIFICATIONS
Unless otherwise noted, AVDD1 = -3.3 V ± 5%, AVDD2 = -3.8 to -5V, AVDD3 = 3.3 V ± 5%, GND = 0 V. Power in dBm is referred to 50 Ω, TA = 25OC; device is programmed to max. channel gain and standard bias conditions1.
Table 2. SPI Timing Parameter Min Typ Max Unit Condition
SERIAL PORT INTERFACE Maximum Clock Rate (tSCLK) 25 MHz Minimum Pulse Width High (tPWH) 20 ns Minimum Pulse Width Low (tPWL) 20 ns Setup Time, SDIO to SCLK (tDS) 5 ns Hold Time, SDIO to SCLK (tDH) 5 ns Data Valid, SDO to SCLK (tDV) 5 ns Setup Time, CSB to SCLK (tDCS) 10 ns Rise Time (tR) 20 ns Applies to SDIO, SDO loaded with 80 pF, 10% to 90% Fall Time (tF) 20 ns Applies to SDIO, SDO loaded with 80 pF, 10% to 90%
Timing Diagram
Figure 2. Serial Port Interface Register Timing, MSB First Figure 3. Timing Diagram for the Serial Port Interface Register Write Figure 4. Timing Diagram for Serial Port Interface Register Read Rev. PrF | Page 6 of 51 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Specifications Timing Diagram SPI Block Write Mode Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Changes from Previous Silicon Revision T/R switch driver output External PA and LNA bias DACs Eliminated the -3.3V supply input to the chip New PA_ON input pin Applications Gain Control Registers Switched Attenuator Control TR_SW_POS and TR_SW_NEG (T/R Switch Control) TX/RX Subcircuit Control TR_SOURCE = 0 SPI Programming Example Register Maps Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Outline Dimensions
Unless otherwise noted, AVDD1 = -3.3 V ± 5%, AVDD2 = -3.8 to -5V, AVDD3 = 3.3 V ± 5%, GND = 0 V. Power in dBm is referred to 50 Ω, TA = 25OC; device is programmed to max. channel gain and standard bias conditions1.
Table 2. SPI Timing Parameter Min Typ Max Unit Condition
SERIAL PORT INTERFACE Maximum Clock Rate (tSCLK) 25 MHz Minimum Pulse Width High (tPWH) 20 ns Minimum Pulse Width Low (tPWL) 20 ns Setup Time, SDIO to SCLK (tDS) 5 ns Hold Time, SDIO to SCLK (tDH) 5 ns Data Valid, SDO to SCLK (tDV) 5 ns Setup Time, CSB to SCLK (tDCS) 10 ns Rise Time (tR) 20 ns Applies to SDIO, SDO loaded with 80 pF, 10% to 90% Fall Time (tF) 20 ns Applies to SDIO, SDO loaded with 80 pF, 10% to 90%
Timing Diagram
Figure 2. Serial Port Interface Register Timing, MSB First Figure 3. Timing Diagram for the Serial Port Interface Register Write Figure 4. Timing Diagram for Serial Port Interface Register Read Rev. PrF | Page 6 of 51 Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Specifications Timing Diagram SPI Block Write Mode Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Changes from Previous Silicon Revision T/R switch driver output External PA and LNA bias DACs Eliminated the -3.3V supply input to the chip New PA_ON input pin Applications Gain Control Registers Switched Attenuator Control TR_SW_POS and TR_SW_NEG (T/R Switch Control) TX/RX Subcircuit Control TR_SOURCE = 0 SPI Programming Example Register Maps Address: 0x000, Reset: 0x00, Name: INTERFACE_CONFIG_A Outline Dimensions