Datasheet AD8340 (Analog Devices) - 3

Data Sheet AD8340 SPECIFICATIONS
VS = 5 V, TA = 25°C, ZO = 50 Ω, f = 880 MHz, single-ended, ac-coupled source drive to RFIP through 5.6 nH series inductor, RFIM ac-coupled through 5.6 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun.
Table 1. Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION Frequency Range 700 1000 MHz Maximum Gain Maximum gain setpoint for all phase setpoints −2 dB Minimum Gain VBBI = VBBQ = 0 V −32 dB Gain Control Range Relative to maximum gain 30 dB Phase Control Range Over 30 dB control range 360 Degrees Gain Flatness Over any 60 MHz bandwidth 0.25 dB Group Delay Flatness Over any 60 MHz bandwidth 10 ps RF INPUT STAGE RFIM, RFIP (Pin 21 and Pin 22) Input Return Loss From RFIP to CMRF (with 5.6 nH series inductors) 20 dB CARTESIAN CONTROL INTERFACE (I and Q) IBBP, IBBM, QBBP, QBBM (Pin 16, Pin 15, Pin 3, Pin 4) Gain Scaling 2 1/V Modulation Bandwidth 250 mV p-p sinusoidal baseband input single-ended 230 MHz Second Harmonic Distortion 250 mV p-p, 1 MHz, sinusoidal baseband input differential 47 dBc Third Harmonic Distortion 250 mV p-p, 1 MHz, sinusoidal baseband input differential 45 dBc Step Response For gain setpoint from 0.1 to 0.9 45 ns (VBBP = 0.5 V, VBBM = 0.55 V to 0.95 V) For gain setpoint from 0.9 to 0.1 47 ns (VBBP = 0.5 V, VBBM = 0.95 V to 0.55 V) RF OUTPUT STAGE RFOP, RFOM (Pin 9 and Pin 10) Output Return Loss Measured through balun 7.5 dB f = 880 MHz Gain Maximum gain setpoint −2 dB Output Noise Floor Maximum gain setpoint, no input −149 dBm/Hz PIN = 0 dBm, frequency offset = 20 MHz −147 dBm/Hz Output IP3 f1 = 880 MHz, f2 = 877.5 MHz, maximum gain setpoint 24 dBm ACPR IS-95, single carrier, POUT = 0 dBm, maximum gain, 62 dBc phase setpoint = 45° Output 1 dB Compression Point Maximum gain 11 dBm POWER SUPPLY VPS2 (Pin 5, Pin 6, Pin 14); RFOP, RFOM (Pin 9 and Pin 10) Positive Supply Voltage 4.75 5 5.25 V Total Supply Current Includes load current 110 130 150 mA OUTPUT DISABLE DSOP (Pin 13) Disable Threshold 2.5 V Maximum Attenuation DSOP = 5 V 40 dB Enable Response Time Delay following high-to-low transition until device 15 ns meets full specifications Disable Response Time Delay following low-to-high transition until device 10 ns produces full attenuation Rev. C | Page 3 of 20 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Quadrature Generator I-Q Attenuators and Baseband Amplifiers Output Amplifier Noise and Distortion Gain and Phase Accuracy RF Frequency Range Applications Information Using the AD8340 RF Input and Matching RF Output and Matching Driving the I-Q Baseband Controls Interfacing to High Speed DACs CDMA2000 Application Evaluation Board Schematic and Artwork Outline Dimensions Ordering Guide