Datasheet LT3957A (Analog Devices) - 10

LT3957A
APPLICATIONS INFORMATION
undervoltage (UV) threshold is 2.7V (typical), with 0.1V recommended that INTVCC pin be shorted to the VIN pin if hysteresis, to ensure that the internal MOSFET has suf- VIN is lower than 3.5V at 1MHz switching frequency, or VIN ficient gate drive voltage before turning on. When INTVCC is lower than 3.2V at 100kHz switching frequency. With is below the UV threshold, the internal power switch will the INTVCC pin shorted to VIN, however, a small current be turned off and the soft-start operation will be triggered. (around 16μA) will load the INTVCC in shutdown mode. The logic circuitry within the LT3957A is also powered D from the internal INTV VCC RVCC CC supply. V INTV OUT CC The INTVCC regulator must be bypassed to SGND imme- LT3957A CVCC diately adjacent to the IC pins with a minimum of 4.7μF 4.7μF ceramic capacitor. Good bypassing is necessary to sup- SGND ply the high transient currents required by the MOSFET 3957A F02 gate driver.
Figure 2. Connecting INTVCC to VOUT
In an actual application, most of the IC supply current is used to drive the gate capacitance of the internal power
Operating Frequency and Synchronization
MOSFET. The on-chip power dissipation can be significant when the internal power MOSFET is being driven at a high The choice of operating frequency may be determined frequency and the VIN voltage is high. by on-chip power dissipation (a low switching frequency may be required to ensure IC junction temperature does An effective approach to reduce the power consumption of not exceed 125°C), otherwise it is a trade-off between the internal LDO for gate drive and to improve the efficiency efficiency and component size. Low frequency operation is to tie the INTVCC pin to an external voltage source high improves efficiency by reducing gate drive current and enough to turn off the internal LDO regulator. MOSFET and diode switching losses. However, lower In SEPIC or flyback applications, the INTVCC pin can be frequency operation requires a physically larger induc- connected to the output voltage VOUT through a blocking tor. Switching frequency also has implications for loop diode, as shown in Figure 2, if VOUT meets the following compensation. The LT3957A uses a constant-frequency conditions: architecture that can be programmed over a 100kHz to 1. V 1000kHz range with a single external resistor from the RT OUT < VIN (pin voltage) pin to SGND, as shown in Figure 1. A table for selecting 2. VOUT < 8V the value of RT for a given operating frequency is shown A resistor R in Table 1. VCC can be connected, as shown in Figure 2, to limit the inrush current from VOUT. Regardless of whether
Table 1. Timing Resistor (RT) Value
or not the INTVCC pin is connected to an external voltage
SWITCHING FREQUENCY (kHz) RT (kΩ)
source, it is always necessary to have the driver circuitry 100 140 bypassed with a 4.7μF low ESR ceramic capacitor to ground 200 63.4 immediately adjacent to the INTVCC and SGND pins. 300 41.2 If LT3957A operates at a low VIN and high switching fre- 400 30.9 quency, the voltage drop across the drain and the source 500 24.3 of the LDO PMOS (M2 in Figure 1) could push INTVCC to 600 19.6 be below the UV threshold. To prevent this from happening, 700 16.5 the INTVCC pin can be shorted directly to the VIN pin. VIN 800 14 must not exceed the INTVCC Absolute Maximum Rating 900 12.1 (8V). In this condition, the internal LDO will be turned off and the gate driver will be powered directly from V 1000 10.5 IN. It is 3957afa 10